CY7C955 データシートの表示（PDF） - Cypress Semiconductor
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CY7C955 Datasheet PDF : 78 Pages
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PRELIMINARY
CY7C955
Transmit Utopia Interface (continued)
Name
TCA
Pin
I/O
86
Output
Description
Transmit Utopia Cell Available: An active state on this signal indicates that the Transmit
FIFO can accept at least N more cells (53 octets) of data where N and the active state
of the signal (HIGH or LOW) are programmable through the configuration registers
(Reg−63H and Reg−01H). In a special case, if Reg–63H bit2−3 is set to 00, Reg−01H,
bit 3 is set to 0, and TCALEVEL0 (Reg–63H, bit 1) set to 0. TCA will behave as an
active HIGH FULL indicator.
Transmit ATM Interface
Name
XOFF
Pin
I/O
50
Input
TGFC
52
Input
TCP
51
Output
Description
Transmit Idle Cell: A HIGH state on this pin will force the ATM Cell Processor to send
an IDLE cell even if there are cells to send in the Transmit FIFO. XOFF is an asynchro-
nous input and has an integrated pull down resistor.
Transmit Generic Flow Control: This bit serial input provides the ability to overwrite the
four bits of the ATM cell header GFC field. These bits may be optionally written during
the four TCLK clock periods following the assertion of the TCP output.
Transmit Start Of GFC: This indicates that the first bit of the GFC for the next cell read
from the Transmit FIFO is expected on the TGFC pin during the next rising edge of
TCLK.
Transmit Clock Generator
Name
TRCLK±
TXC±
TXD±
TBYP
RATE0
RATE1
TCLK
TFPO
Pin
9−10
13−14
15−16
2
97−98
54
53
I/O
Differential In
Differential Out
Differential Out
Input
Input
Output
Output
Description
Transmit Input Clock: Accepts either a differential PECL, or a TTL or a CMOS byte rate
reference connected to TRCLK− with TRCLK+ grounded for the Transmit frequency
multiplier PLL. Optionally, this input can accept also the bit rate reference when TBYP
is true (held HIGH). In this mode the Transmit frequency multiplier is bypassed and the
bit rate clock is used directly for transmit side clocking.
Transmit Output Clock: Provides clock output for the transmit data. TXD± is updated
on the falling edge of this signal. In the default setting, TXC is disabled if RATE0 is
HIGH and a 51.84-MHz clock if RATE0 is LOW. XORTXC (Reg−04H, bit 6) can be used
to invert the default setting such that TXC is a 155.52-MHz clock if RATE0 is HIGH and
is disabled when RATE0 is LOW.
Transmit Data Output: Accepts NRZ encoded output data. This signal is updated on
the falling edge of TXC±.
Transmit Clock Bypass: When this input is held HIGH the transmit frequency multiplier
is disabled and TRCLK± input is used directly for transmit side clocking. When this input
is held LOW the transmit frequency multiplier multiplies the TRCLK± input by 8, 24, or
8/3 (depending on the TREFSEL (Reg−06H, bit 0) setting to provide the internal bit
rate clock.
RATE: When the RATE0 input is HIGH the Transmit frequency generator and the Re-
ceive clock recovery are selected to operate at the STS−3c/STM−1 rate of 155.52 MHz.
When the RATE0 pin is LOW, the Transmit frequency generator and the Receive clock
recovery are selected to operate at the STS−1 rate of 51.84 MHz. RATE1 is for factory
testing use only and should be tied HIGH. Both RATE0 and RATE1 have integrated
pull-up resistors.
Transmit Byte Reference: Byte rate reference clock derived from the transmit line bit
rate.
Transmit Frame Reference. This signal is an 8-kHz frame rate reference that goes
HIGH during the transmission of the first A1 byte of the SONET/SDH frame. TFPO is
updated by the rising edge of TCLK.
Receive Clock Recovery
Name
RXD±
Pin
I/O
25−26 Differential In
Description
Receive Input Data: These line receiver inputs are connected to an internal Receive
PLL that recovers the embedded clock and data information. The incoming data rate
can be within one of two frequency ranges depending on the state of the RATE0 pin.
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