MCM62110FN20 データシートの表示（PDF） - Motorola => Freescale
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MCM62110FN20
Motorola => Freescale
MCM62110FN20 Datasheet PDF : 12 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ CYCLE (See Note 1)
MCM62110–15 MCM62110–17 MCM62110–20
Parameter
Symbol
Min Max Min Max Min Max Unit Notes
Read Cycle Time Clock High to Clock High
tKHKH
15
—
17
—
20
—
ns 1, 2
Clock Low Pulse Width
tKLKH
5
—
5
—
5
—
ns
Clock High Pulse Width
tKHKL
7
—
7
—
7
—
ns
Clock High to DPE Valid
tKHDPEV
—
7
—
8
—
10
ns
5
Clock High to Output Valid
tKHQV
—
7
—
7.5
—
10
ns 4, 3
Clock (K) High to Output Low Z After Write
tKHQX1
8
—
8
—
8
—
ns
Output Hold from Clock High
tKHQX2
5
—
5
—
5
—
ns 4, 6
Clock High to Q High–Z (E1 or E2 = False)
tKHQZ
—
8
—
9
—
10
ns
6
Setup TImes:
A
tAVKL
2.5
—
2.5
—
2.5
—
ns
W tWHKH
E1, E2
tEVKL
PIE tPIEHKH
SIE tSIEHKH
POE tPOEVKH
7
SOE tSOEVKH
7
Hold Times:
A
tKLAX
2
—
2
—
2
—
ns
W tKHWX
E1, E2
tKLEX
PIE tKHPIEX
SIE tKHSIEX
POE tKHPOEX
7
SOE tKHSOEX
7
Output Enable High to Q High–Z
tPOEHQZ
0
8
0
9
0
9
ns
6
tSOEHQZ
Output Hold from Output Enable High
tPOEHQX
5
—
5
—
5
—
ns
6
tSOEHQX
Output Enable Low to Q Active
tPOELQX
0
—
0
—
0
—
ns
6
tSOELQX
Output Enable Low to Output Valid
tPOELQV
—
5
—
6
—
8
ns
tSOELQV
NOTES:
1. A read is defined by W high for the setup and hold times.
2. All read cycle timing is referenced from K, SOE, or POE.
3. Access time is controlled by tKLQV if the clock low pulse width is less than (tKLQV–tKHQV); otherwise it is controlled by KHQV.
4. K must be at a high level for outputs to transition.
5. DPE is valid exactly one clock cycle after the output data is valid.
6. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tKHQZ is less than tKHQX, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less
than tSOELQX for a given device.
7. These read cycle timings are used to guarantee proper parity operation only.
MOTOROLA FAST SRAM
MCM62110
5
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