MCM62110FN20 データシートの表示（PDF） - Motorola => Freescale
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MCM62110FN20
Motorola => Freescale
MCM62110FN20 Datasheet PDF : 12 Pages
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BLOCK DIAGRAM
K
A0 – A14
32K × 9 ARRAY
DPE
DATA
REGISTER
PARITY
CHECK
WRITE
DRIVER
PDQ0 – PDQ7, PDQP
POE
DATA
REGISTER
9
DATA
LATCH
9
SENSE
DATA
DATA
AMPLIFIER
LATCH
REGISTER
W
E1
E2
9
PIE
SIE
SDQ0 – SDQ7, SDQP
SOE
FUNCTIONAL TRUTH TABLE (See Notes 1 and 2)
Memory Subsystem
W PIE SIE POE SOE Mode
Cycle
1
1
1
0
1
Read
Processor Read
1
1
1
1
0
Read
Copy Back
1
1
1
0
0
Read
Dual Bus Read
1
X
X
1
1
Read
NOP
X
0
0
X
X
N/A
NOP
0
0
1
1
1
Write
Processor Write Hit
0
1
0
1
1
Write
Allocate
0
0
1
1
0
Write
Write Through
0
1
0
0
1
Write
Allocate With Stream
1
0
1
1
0
N/A
Cache Inhibit Write
1
1
0
0
1
N/A
Cache Inhibit Read
0
1
1
X
X
N/A
NOP
X
0
1
0
0
N/A
Invalid
X
0
1
0
1
N/A
Invalid
X
1
0
0
0
N/A
Invalid
X
1
0
1
0
N/A
Invalid
PDQ0 – PDQ7,
PDQP Output
Data Out
High–Z
Data Out
High–Z
High–Z
Data In
High–Z
Data In
Stream Data
Data In
Stream Data
High–Z
Data In
Data In
Stream
High–Z
SDQ0 – SDQ7,
SDQP Output
High–Z
Data Out
Data Out
High–Z
High–Z
High–Z
Data In
Stream Data
Data In
Stream Data
Data In
High–Z
Stream
High–Z
Data In
Data In
DPE
Parity Out
Parity Out
Parity Out
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes
3, 4
3, 4
3, 4
2, 5
2, 6
2
2, 7
2, 7
2, 7
2, 7
5
2, 8
2, 8
2, 8
2, 8
NOTES:
1. A ‘0’ represents an input voltage ≤ VIL and a ‘1’ represents an input voltage ≥ VIH. All inputs must satisfy the specified setup and hold times
for the falling or rising edge of K. Some entries in this truth table represent latched values. This table assumes that the chip is selected (i.e.,
E1 = 0 and E2 = 1) and VCC current is equal to ICCA. If this is not true, the chip will be in standby mode, the VCC current will equal ISB1 or ISB2
DPE will default to 1 and all RAM outputs will be in High–Z. Other possible combinations of control inputs not covered by this note or the table
above are not supported and the RAM’s behavior is not specified.
2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don’t care, and the corresponding outputs are High–Z.
3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM.
4. DPE is registered on the rising edge of K at the beginning of the following clock cycle
5. No RAM cycle is performed.
6. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 – PDQ7 and PDQP
or SDQ0 – SDQ7 and SPDQ), and written into the RAM.
7. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other I/O
port.
8. Data contention will occur.
MCM62110
2
MOTOROLA FAST SRAM
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