CY7C4265-35AI データシートの表示（PDF） - Cypress Semiconductor

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CY7C4265-35AI

8K/16K x 18 Deep Sync FIFOs

Cypress Semiconductor 

Switching Waveforms

Write Cycle Timing

WCLK

tCLKH

tCLK

D0 –D17

WEN

FF

RCLK

tWFF

tSKEW1 [14]

tCLKL

tDS

tENS

CY7C4255

CY7C4265

tDH

tENH

tWFF

NO OPERATION

REN

Read Cycle Timing

RCLK

REN

tENS

EF

Q0 –Q17

OE

WCLK

tOLZ

tCLKH

tCLK

tCLKL

tENH

tREF

NO OPERATION

tA

tOE

tSKEW2[15]

tREF

VALID DATA

tOHZ

4255–6

WEN

4255–7

Notes:

14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.

15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between

the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.

7

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