CY7C4265-35AI データシートの表示（PDF） - Cypress Semiconductor

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CY7C4265-35AI

8K/16K x 18 Deep Sync FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))

tCLKH

tCLKL

WCLK

WEN

tENS tENH

CY7C4255

CY7C4265

WEN2

PAE

RCLK

REN

tENS tENH

tSKEW3 [22]

Note

21

tPAE synch

N + 1 WORDS

INFIFO

tENS

tENS tENH

Programmable Almost Full Flag Timing

Note

23

tPAE synch

4255–14

WCLK

WEN

tCLKH

Note 24

tCLKL

tENS tENH

PAF [25]

RCLK

REN

tPAF

FULL– M WORDS

INFIFO [26]

FULL– (M+1) WORDS

IN FIFO[27]

tPAF

tENS

4255–15

Notes:

21. PAE offset − n.

22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and

the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.

23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.

24. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265.

25. PAF is offset = m.

26. 8192 − m words in CY7C4255 and 16384 – m words in CY7C4265.

27. 8192 − (m + 1) words in CY7C4255 and 16384 – (m + 1) CY7C4265.

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