CY7C4255V(2001) データシートの表示（PDF） - Cypress Semiconductor

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CY7C4255V
(Rev.:2001)

32K/64Kx18 Low Voltage Deep Sync FIFOs

Cypress Semiconductor 

Switching Waveforms

Write Cycle Timing

WCLK

tCLKH

tCLK

D0 –D17

WEN

FF

RCLK

tWFF

tSKEW1 [13]

tCLKL

tDS

tENS

CY7C4255V/CY7C4265V

CY7C4275V/CY7C4285V

tDH

tENH

tWFF

NO OPERATION

REN

Read Cycle Timing

RCLK

REN

tENS

EF

Q0 –Q17

OE

WCLK

tOLZ

tCLKH

tCLK

tCLKL

tENH

tREF

tA

NO OPERATION

tOE

tSKEW2[14]

tREF

VALID DATA

tOHZ

4275V–8

WEN

4275V–9

Notes:

13. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the

rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.

14. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the

rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.

Document #: 38-06012 Rev. **

Page 7 of 20

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