CY7C4255V(2001) データシートの表示（PDF） - Cypress Semiconductor
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CY7C4255V Datasheet PDF : 20 Pages
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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Characteristics Over the Operating Range (continued)
7C4255/65/75/85V 7C4255/65/75/85V 7C4255/65/75/85V
-10
-15
-25
Parameter
tOHZ
tWFF
tREF
tPAFasynch
tPAFsynch
tPAEasynch
tPAEsynch
tHF
tXO
tXI
tXIS
tSKEW1
Description
Output Enable to Output in High Z[11]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full
Flag[12] (Asynchronous mode,
VCC/SMODE tied to VCC)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to
VSS)
Clock to Programmable Almost-Empty
Flag[12] (Asynchronous mode, VCC/SMODE
tied to VCC)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to
VSS)
Clock to Half-Full Flag
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-Up Time
Skew Time between Read Clock and
Write Clock for Full Flag
tSKEW2
Skew Time between Read Clock and
Write Clock for Empty Flag
tSKEW3
Skew Time between Read Clock and
Write Clock for Programmable Almost
Empty and Programmable Almost Full
Flags (Synchronous Mode only)
Min.
3
4.5
4
5
5
10
Max.
7
8
8
15
8
15
8
12
6
Min.
3
6.5
5
6
6
15
Max.
8
10
10
16
10
16
10
16
10
Min.
3
10
10
10
10
18
Max. Unit
12
ns
15
ns
15
ns
20
ns
15
ns
20
ns
15
ns
20
ns
15
ns
ns
ns
ns
ns
ns
Note:
12. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
Document #: 38-06012 Rev. **
Page 6 of 20
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