LC680100A データシートの表示（PDF） - SANYO -> Panasonic

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LC680100A

32-Bit RISC Microcontroller

SANYO -> Panasonic 

Pin Number

Pin Name

33

NMI

35

P10/BGNT

36

P11/RAS

37

P12/CASU

38

P13/CASL

39

P14/DMXS

40

P15/RFREQ

41

P16/IRQOT

42

P17/MCLK/HOLD0

44

45 to 54,

56 to 69

70

71

72

74 to 81,

83 to 90

92

93

94

95

96

97

98

99

100

A0/LBS

A1to A24

A25/CS5

A26/CS4

A27/CS3

D0 to D15

CS0

CS1

CS2

CS6

RD

WRU/UBS

WRL/WR

WAIT

BREQ

LC680100A

I/O

Function Description

I NMI interrupt

I/O PORT1 bit0 input.

Also bus grant output.

I/O PORT1 bit1 input. Also

DRAM control RAS signal out.

I/O PORT1 bit2 input. Also

DRAM control CASU signal out.

I/O PORT1 bit3 input. Also

DRAM control CASL signal out.

I/O PORT1 bit4 input. Also

DRAM control DMXS signal out.

I/O PORT1 bit5 input. Also

DRAM control RFREQ I/O.

I/O PORT1 bit6 input.

Also IRQOT output.

I/O PORT1 bit7 input.

MCLK output,

HOLD state output

I/O Bus Address bit0 or

Lower byte strobe signal.

I/O Bus Address bit1 to 24.

Pin Format

Schmitt Input

Schmitt Input•Tristate

output

Schmitt Input•PU

Output

Schmitt Input•Tristate

output

Schmitt Input•Tristate

output

I/O Bus Address bit25 or CS5.

I/O Bus Address bit26 or CS4

I/O Bus Address bit27 or CS3.

I/O Bus data bit0 to 15

Schmitt Input•Tristate

output

I/O CS0

I/O CS1

Schmitt Input•Tristate

output

I/O CS2

I/O CS6

I/O Bus read signal.

Schmitt Input•Tristate

output

I/O Upper byte write signal or Upper byte strobe.

I/O Upper byte write signal or Write.

I/O Bus cycle wait

I Bus request.

Schmitt Input•PU

output

Schmitt Input

No.6830-5/16

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