CY7C1215H データシートの表示（PDF） - Cypress Semiconductor
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CY7C1215H Datasheet PDF : 15 Pages
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CY7C1215H
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
00
Second
Address
A1, A0
01
Third
Address
A1, A0
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Truth Table[2, 3, 4, 5, 6]
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
40
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Next Cycle Add. Used ZZ CE1 CE2 CE3 ADSP ADSC ADV OE
DQ
Write
Unselected
None
L
H
XX
X
L
X
X
Tri-State
X
Unselected
None
L
L
XH
L
X
X
X
Tri-State
X
Unselected
None
L
L
LX
L
X
X
X
Tri-State
X
Unselected
None
L
L
XH
H
L
X
X
Tri-State
X
Unselected
None
L
L
LX
H
L
X
X
Tri-State
X
Begin Read
External
L
L
HL
L
X
X
X
Tri-State
X
Begin Read
External
L
L
HL
H
L
X
X
Tri-State Read
Continue Read
Next
L
X
XX
H
H
L
H
Tri-State Read
Continue Read
Next
L
X
XX
H
H
L
L
DQ
Read
Continue Read
Next
L
H
XX
X
H
L
H
Tri-State Read
Continue Read
Next
L
H
XX
X
H
L
L
DQ
Read
Suspend Read
Current
L
X
XX
H
H
H
H
Tri-State Read
Suspend Read
Current
L
X
XX
H
H
H
L
DQ
Read
Suspend Read
Current
L
H
XX
X
H
H
H
Tri-State Read
Suspend Read
Current
L
H
XX
X
H
H
L
DQ
Read
Begin Write
Current
L
X
XX
H
H
H
X
Tri-State Write
Begin Write
Current
L
H
XX
X
H
H
X
Tri-State Write
Begin Write
External
L
L
HL
H
H
X
X
Tri-State Write
Continue Write
Next
L
X
XX
H
H
H
X
Tri-State Write
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05666 Rev. *B
Page 5 of 15
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