CY2305C データシートの表示（PDF） - Cypress Semiconductor

部品番号

コンポーネント説明

一致するリスト

CY2305C

3.3 V Zero Delay Clock Buffer

Cypress Semiconductor 

CY2305C

CY2309C

Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX

Switching characteristics table for CY2305CSXC-1H and CY2309CSXC-1H commercial temperature devices. All parameters are

specified with loaded outputs.

Parameter

Name

Description

Min

t1

Output frequency

30-pF load

10

10-pF load

10

tDC

Output duty cycle[11] = t2  t1 Measured at 1.4 V, Fout > 50 MHz

40

Measured at 1.4 V, Fout  50 MHz

45

t3

Rise time[11]

Measured between 0.8 V and 2.0 V

–

t4

Fall time[11]

Measured between 0.8 V and 2.0 V

–

t5

Output-to-output skew[11] All outputs equally loaded

–

t6A

Delay, REF rising edge to

CLKOUT rising edge[11]

Measured at VDD/2

–

t6B

t7

t8

tJ

tLOCK

Delay, REF rising edge to

CLKOUT rising edge[11]

Measured at VDD/2. Measured in PLL

Bypass mode, CY2309C device only.

1

Device-to-device skew[11] Measured at VDD/2 on the CLKOUT pins

–

of devices

Output slew rate[11]

Measured between 0.8 V and 2.0 V using

1

Test circuit #2

Cycle-to-cycle jitter, peak[11] Measured at 66.67 MHz, loaded outputs

–

PLL lock time[11]

Stable power supply, valid clock

–

presented on REF pin

Typ

Max

Unit

–

100

MHz

133.33 MHz

50

60

%

50

55

%

–

1.5

ns

–

1.5

ns

–

200

ps

0

±350

ps

5

8.7

ns

0

700

ps

–

–

V/ns

–

175

ps

–

1.0

ms

Switching Characteristics for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX

Switching characteristics table for CY2305CSXI-1, CY2305CSXA-1, and CY2309CSXI-1 industrial temperature devices. All

parameters are specified with loaded outputs.

Parameter

Name

Test Conditions

Min

t1

Output frequency

30 pF load

10

10 pF load

10

tDC

Output duty cycle[11] = t2  t1 Measured at 1.4 V, Fout > 50 MHz

40

Measured at 1.4 V, Fout <= 50 MHz

45

t3

Rise time[11]

Measured between 0.8 V and 2.0 V

–

t4

Fall time[11]

Measured between 0.8 V and 2.0 V

–

t5

Output-to-output skew[11]

All outputs equally loaded

–

t6A

Delay, REF rising edge to

CLKOUT rising edge[11]

Measured at VDD/2

–

t6B

t7

tJ

tLOCK

Delay, REF rising edge to

CLKOUT rising edge[11]

Measured at VDD/2. Measured in PLL

Bypass mode, CY2309C device only.

1

Device-to-device skew[11]

Measured at VDD/2 on the CLKOUT pins

–

of devices

Cycle-to-cycle jitter, peak[11] Measured at 66.67 MHz, loaded outputs

–

PLL lock time[11]

Stable power supply, valid clock

–

presented on REF pin

Typ

Max

Unit

–

100

MHz

133.33

MHz

50

60

%

50

55

%

–

2.25

ns

–

2.25

ns

–

200

ps

0

±350

ps

5

8.7

ns

0

700

ps

50

175

ps

–

1.0

ms

Note

11. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Document Number: 38-07672 Rev. *K

Page 8 of 17

[+] Feedback

Share Link: