CY2305C データシートの表示（PDF） - Cypress Semiconductor

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CY2305C

3.3 V Zero Delay Clock Buffer

Cypress Semiconductor 

Pinouts

CY2305C

Figure 1. Pin Diagram - 8 Pin SOIC (Top View)

REF

CLK2

CLK1

GND

1

8

2 CY2305C 7

3

6

4

5

CLKOUT

CLK4

VDD

CLK3

Table 1. Pin Description - 8 Pin SOIC

Pin

Signal

1

REF[1]

2

CLK2[2]

3

CLK1[2]

4

GND

5

CLK3[2]

6

VDD

7

CLK4[2]

8

CLKOUT[2]

Description

Input reference frequency

Buffered clock output

Buffered clock output

Ground

Buffered clock output

3.3 V supply

Buffered clock output

Buffered clock output, internal feedback on this pin

CY2309C

Figure 2. Pin Diagram - 16 Pin SOIC/TSSOP (Top View)

REF

CLKA1

CLKA2

VDD

GND

CLKB1

CLKB2

S2

1

16

2CY2309C 15

3

14

4

13

5

12

6

11

7

10

8

9

CLKOUT

CLKA4

CLKA3

VDD

GND

CLKB4

CLKB3

S1

Table 2. Pin Definition - 16 Pin SOIC/TSSOP

Pin

Signal

1

REF[1]

2

CLKA1[2]

3

CLKA2[2]

4

VDD

5

GND

6

CLKB1[2]

7

CLKB2[2]

8

S2[3]

Input reference frequency

Buffered clock output, Bank A

Buffered clock output, Bank A

3.3 V supply

Ground

Buffered clock output, Bank B

Buffered clock output, Bank B

Select input, bit 2

Description

Notes

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs

Document Number: 38-07672 Rev. *K

CY2305C

CY2309C

Page 4 of 17

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