CY22393 データシートの表示（PDF） - Cypress Semiconductor

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CY22393

Three-PLL Serial-Programmable Flash-Programmable Clock Generator

Cypress Semiconductor 

CY22393

CY22394

CY22395

Start Sequence - Start Frame is indicated by SDAT going LOW

when SCLK is HIGH. Every time a start signal is given, the next

8-bit data must be the device address (seven bits) and a R/W

bit, followed by register address (eight bits) and register data

(eight bits).

Stop Sequence - Stop Frame is indicated by SDAT going HIGH

when SCLK is HIGH. A Stop Frame frees the bus for writing to

another part on the same bus or writing to another random

register address.

Acknowledge Pulse

During Write Mode the CY22393, CY22394, and CY22395

respond with an Acknowledge pulse after every eight bits. To

do this, they pull the SDAT line LOW during the N*9th clock

cycle, as illustrated in Figure 5 on page 11. (N = the number of

bytes transmitted). During Read Mode, the master generates

the acknowledge pulse after the data packet is read.

Write Operations

Writing Individual Bytes

A valid write operation must have a full 8-bit register address

after the device address word from the master, which is

followed by an acknowledge bit from the slave (ack = 0/LOW).

The next eight bits must contain the data word intended for

storage. After the data word is received, the slave responds

with another acknowledge bit (ack = 0/LOW), and the master

must end the write sequence with a STOP condition.

Writing Multiple Bytes

To write multiple bytes at a time, the master must not end the

write sequence with a STOP condition. Instead, the master

sends multiple contiguous bytes of data to be stored. After

each byte, the slave responds with an acknowledge bit, the

same as after the first byte, and accepts data until the STOP

condition responds to the acknowledge bit. When receiving

multiple bytes, the CY22393, CY22394, and CY22395 inter-

nally increment the register address.

Read Operations

Read operations are initiated the same way as Write opera-

tions except that the R/W bit of the slave address is set to ‘1’

(HIGH). There are three basic read operations: current

address read, random read, and sequential read.

Current Address Read

The CY22393, CY22394 and CY22395 have an onboard

address counter that retains “1” more than the address of the

last word access. If the last word written or read was word ‘n’,

then a current address read operation returns the value stored

in location ‘n+1’. When the CY22393, CY22394 and CY22395

receive the slave address with the R/W bit set to a ‘1’, they

issue an acknowledge and transmit the 8-bit word. The master

device does not acknowledge the transfer, but generates a

STOP condition, which causes the CY22393, CY22394 and

CY22395 to stop transmission.

Random Read

Through random read operations, the master may access any

memory location. To perform this type of read operation, first

set the word address. Do this by sending the address to the

CY22393, CY22394 and CY22395 as part of a write operation.

After the word address is sent, the master generates a START

condition following the acknowledge. This terminates the write

operation before any data is stored in the address, but not

before setting the internal address pointer. Next, the master

reissues the control byte with the R/W byte set to ‘1’. The

CY22393, CY22394 and CY22395 then issue an acknowledge

and transmit the 8-bit word. The master device does not

acknowledge the transfer, but generates a STOP condition

which causes the CY22393, CY22394 and CY22395 to stop

transmission.

Sequential Read

Sequential read operations follow the same process as

random reads except that the master issues an acknowledge

instead of a STOP condition after transmitting the first 8-bit

data word. This action increments the internal address pointer,

and subsequently outputs the next 8-bit data word. By

continuing to issue acknowledges instead of STOP conditions,

the master serially reads the entire contents of the slave

device memory. Note that register addresses outside of 08H

to 1BH and 40H to 57H can be read from but are not real

registers and do not contain configuration information. When

the internal address pointer points to the FFH register, after the

next increment, the pointer will point to the 00H register.

Figure 1. Data Transfer Sequence on the Serial Bus

SCLK

SDAT

START

Condition

Address or

Acknowledge

Valid

Data may

be changed

STOP

Condition

Document #: 38-07186 Rev. *C

Page 9 of 17

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