CY22393 データシートの表示（PDF） - Cypress Semiconductor
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CY22393 Datasheet PDF : 17 Pages
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CY22393
CY22394
CY22395
Pin Definitions (continued)
Name
CLKB or LCLKB
CLKA or LCLKA
GND/LGND
SDAT (S0)
SCLK (S1)
AVDD
S2/
SUSPEND
SHUTDOWN/
OE
Pin Number Pin Number Pin Number
CY22393 CY22394 CY22395
Description
9
9
9
Configurable clock output B; LCLKB referenced to LVDD
10
10
10
Configurable clock output A; LCLKA referenced to LVDD
11
11
11
Ground
12
12
12
Serial Port (I2C) Data. S0 value latched during start up
13
13
13
Serial Port (I2C) Clock. S1 value latched during start up
14
14
14
Analog Power Supply
15
15
15
General purpose input for frequency control; bit 2. Optionally,
Suspend mode control input
16
16
16
Places outputs in tri-state condition and shuts down chip when
LOW. Optionally, only places outputs in tri-state condition and
does not shut down chip when LOW
Operation
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The clock family has three PLLs which, when combined with
the reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to two locations: the cross point switch and the PECL output
(CY22394). The output of PLL1 is also sent to a /2, /3, or /4
synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed using serial programming
or by external CMOS inputs, S0, S1, and S2. See the following
section on General Purpose Inputs for more detail.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the cross point switch. The frequency of PLL2 is changed
using serial programming.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross point switch. The frequency of PLL3 is changed
using serial programming.
General Purpose Inputs
S2 is a general purpose input that is programmed to allow for
two different frequency settings. Options that switches with
this general purpose input are as follows: the frequency of
PLL1, the output divider of CLKB, and the output divider of
CLKA.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start up and used as the other two indexes
into this array.
CLKA and CLKB have seven-bit dividers that point to one of
the two programmable settings (register 0 and register 1). Both
clocks share a single register control and both must be set to
register 0, or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Crystal Input
The input crystal oscillator is an important feature of this family
of parts because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, process, performance, and quality.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when nonlinear load
capacitance interacts with load, bias, supply, and temperature
changes. Nonlinear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
For driven clock inputs, the input load capacitors can be
completely bypassed. This allows the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, leave XTALOUT floating.
Document #: 38-07186 Rev. *C
Page 4 of 17
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