CY22150FC データシートの表示（PDF） - Cypress Semiconductor

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CY22150FC

One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator

Cypress Semiconductor 

CY22150

SDAT Write

Multiple

Contiguous

Registers

1-bit 1-bit

1-bit Slave Slave

R/W = 0 ACK ACK

1-bit

Slave

ACK

1-bit

Slave

ACK

7-bit

8-bit 8-bit 8-bit 8-bit

Device Register Register Register Register

Address Address Data Data Data

(XXH) (XXH) (XXH+1) (XXH+2)

Start Signal

1-bit 1-bit 1-bit

Slave Slave Slave

ACK ACK ACK

8-bit 8-bit

Register Register

Data Data

(FFH) (00H)

1-bit

Slave

ACK

Stop Signal

SDAT Read

Multiple

Contiguous

Registers

1-bit 1-bit

1-bit

1-bit Slave Slave 1-bit Master

R/W = 0 ACK ACK R/W = 1 ACK

7-bit

8-bit

8-bit 8-bit

Device Register 7-Bit Register Register

Address Address Device Data Data

(XXH) Address (XXH) (XXH+1)

Start Signal

1-bit 1-bit 1-bit

Master Master Master

ACK ACK ACK

8-bit 8-bit

Register Register

Data Data

(FFH) (00H)

Figure 3. Data Frame Architecture

1-bit

Master

ACK

Stop Signal

START

Transition

to next bit

STOP

Figure 4. Start and Stop Frame

SDAT

SCLK

SDAT

+

+

+

START DA6 DA5DA0 R/W ACK RA7 RA6RA1 RA0 ACK D7 D6 D1 D0 ACK

SCLK

+

+

+

STOP

Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data

Parameter

Description

Min.

Max.

Unit

fSCLK

Frequency of SCLK

Start mode time from SDA LOW to SCL LOW

0.6

400

kHz

µs

CLKLOW

CLKHIGH

SCLK LOW period

SCLK HIGH period

1.3

µs

0.6

µs

tSU

Data transition to SCLK HIGH

100

ns

tDH

Data hold (SCLK LOW to data transition)

0

ns

Rise time of SCLK and SDAT

300

ns

Fall time of SCLK and SDAT

300

ns

Stop mode time from SCLK HIGH to SDAT HIGH

0.6

µs

Stop mode to Start mode

1.3

µs

Document #: 38-07104 Rev. *F

Page 8 of 13

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