CY22150FC データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
一致するリスト
CY22150FC
Cypress Semiconductor
CY22150FC Datasheet PDF : 13 Pages
| |||
CY22150
Table 17. AC Electrical Characteristics
Parameter[7]
Name
Description
Min.
t1
Output Frequency, Clock output limit, 3.3V
Commercial Temp Clock output limit, 2.5V
0.08 (80 kHz)
0.08 (80 kHz)
Output Frequency, Clock output limit, 3.3V
Industrial Temp
Clock output limit, 2.5V
0.08 (80 kHz)
0.08 (80 kHz)
t2LO
Output Duty Cycle Duty cycle is defined in Figure 6; t1/t2
45
fOUT < 166 MHz, 50% of VDD
t2HI
Output Duty Cycle Duty cycle is defined in Figure 6; t1/t2
40
fOUT > 166 MHz, 50% of VDD
t3LO
Rising Edge Slew Output clock rise time, 20% – 80% of VDDL.
0.6
Rate (VDDL = 2.5V) Defined in Figure 7.
t4LO
Falling Edge Slew Output dlock fall time, 80% – 20% of VDDL.
0.6
Rate (VDDL = 2.5V) Defined in Figure 7.
t3HI
Rising Edge Slew Output dlock rise time, 20% – 80% of
0.8
Rate (VDDL = 3.3V) VDD/VDDL. Defined in Figure 7.
t4HI
Falling Edge Slew Output dlock fall time, 80% – 20% of
0.8
Rate (VDDL = 3.3V) VDD/VDDL. Defined in Figure 7.
t5[8]
Skew
Output-output skew between related outputs.
t6[9]
Clock Jitter
Peak-to-peak period jitter
t10
PLL Lock Time
Typ.
50
50
1.2
1.2
1.4
1.4
250
0.30
Max.
200
166.6
166.6
150
55
60
250
3
Unit
MHz
MHz
MHz
MHz
%
%
V/ns
V/ns
V/ns
V/ns
ps
ps
ms
Device Characteristics
Parameter
θJA
Complexity
Name
theta JA
Transistor Count
Value
115
74,600
Unit
°C/W
transistors
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY22150FC
Z16
16-lead TSSOP Commercial (0 to 70°C)
3.3V
CY22150FI
Z16
CY22150ZC-xxx[10] Z16
CY22150ZI-xxx[10]
Z16
16-lead TSSOP
16-lead TSSOP
16-lead TSSOP
Industrial (–40 to 85°C)
Commercial (0 to 70°C)
Industrial (–40 to 85°C)
3.3V
3.3V
3.3V
CY3672
FTG Development System N/A
CY3672ADP000
CY22150F Socket
Notes:
7. Not 100% tested, guaranteed by design.
8. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Diagram for more information.
9. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL, (2.5V or 3.3V jitter in
“PLL-Based Systems: Causes, Effects, and Solutions,” available at http://wwww.cypress.com/clock/appnotes.html, or contact your local Cypress field appli-
cations engineer).
10. The CY22150ZC-xxx and CY22150ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document #: 38-07104 Rev. *F
Page 11 of 13
Share Link: