CDB6403 データシートの表示（PDF） - Cirrus Logic

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CDB6403

Echo-Cancelling Codec

Cirrus Logic 

CDB6403

AGND C8

FE_OUT+

FE_OUT-

1 RO+

2 RO-

J5 3 PI

4 PO-

5 PO+

VAG

20

X7R

0.1 µF

R9

TI+ 19

10k

TI- 18

R2

R10

10k

R3

C9

X7R FE_IN-

0.1 µF

C11

TG 17

U3

MU/A 16

X7R FE_IN+

10k

10k 0.1 µF

UALAW

+5VA

X7R C5

0.1 µF

6 VDD MC145480 VSS 15

7 FSR

FST 14

AGND

SYNCOUT

SDO

8 DR

DT 13

SDI

9 BCLKR

BCLKT 12

SCLK

CONFIG

10 PDI

MCLK 11

Figure 5. On-board PCM Codec

The far-end input gain is determined by R2, R3,

R9, and R10 which are all currently 10kΩ. The

resistors are part of a differential amplifier whose

gain is (-R2/R3). Note that R2 and R9 should

have the same value, as should R3 and R10.

Both FE_IN+ and FE_IN- are connected through

a 0.1µF DC blocking capacitor.

The far-end output drive capability can be

boosted by using the PI, PO+ and PO- pins of

the MC145480. PI and PO- are equivalent to the

inverting input and output, respectively, of an

opamp. PO+ and PO- are differential drivers ca-

pable of driving a 150Ω load. Easy access to PI,

PO-, and PO+ is provided through J5, J6, and J7,

respectively. See the MC145480 datasheet and

Figure 5 for more details.

EPLD

The EMP7032 EPLD from Altera handles some

miscellaneous logic functions on the evaluation

board, but is not necessary for operation. It is

mainly used to encode the Algorithm Control

Switches (SW2-6) to the GPIN2/1/0 pins. It also

buffers the DIP switches, and it provides in-

verters for the LED bank.

The encoding of SW2-6 could have been done

without using programmable logic, but the

EPLD assures that only legal combinations of

buttons are accepted for all modes of operation

of the evaluation board. The EPLD provides the

function of several buffers, inverters, and

AND/OR gates. A Schmitt-trigger inverter U101

is added to provide hardware debouncing of the

switches.

An added benefit of the EPLD is that it demon-

strates effective use of separate ground planes for

analog and digital components. Although all of

the digital logic in the EPLD is relatively static,

the CDB6403 provides a good example of how

to split the digital and analog sides of a board.

Note that the CS6403 resides completely on the

analog side of the board and digital signals cross

the break in the ground planes by taking the

shortest possible route.

DS192DB3

41

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