CDB6403 データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CDB6403

Echo-Cancelling Codec

Cirrus Logic 

CDB6403

FE_OUT is capable of producing 6.3Vpp differ-

entially or 3.15Vpp single-ended. If the

equipment intended to interface to FE_OUT is

capable of accepting a differential input, a resis-

tive divider which attenuates the differential

signal by a factor of 0.89 will be sufficient. If

the equipment requires a ground reference, an

external amplifier providing a gain of 1.78 to the

single-ended signal is necessary.

The full-scale input at MICIN is 2Vpp with the

gain stage off (GPIN3 is high). The gain of the

differential amplifier provided by U100 needs to

be decreased to 0.36 times. Replacing R104

and R105 with 3.6kΩ resistors and changing

C101 to 0.74µF (0.68µF in parallel with

0.068µF) will change the gain appropriately

while maintaining good common-mode rejection

at all frequencies. It is important to make sure

that the opamp is referenced around >2VDC

rather than VCM, as clipping is likely to occur

otherwise. This change is described in the sec-

tion explaining the Microphone Circuitry.

SPKROUT drives 1.75Vpp with respect to

ground out of both SPKROUTP and

SPKROUTN. Even taken differentially, the re-

sulting 3.5Vpp is not enough to reach the

required 5.6Vpp. An external amplifier provid-

ing 3.2 times gain to SPKROUTP is required to

produce the required output signal level.

Troubleshooting Tips

If the CDB6403 is not working properly or is

not working as expected, this list of common

setup problems may help.

General hints:

• Make sure 5VDC is applied to both the digi-

tal and analog supplies.

• RESET the evaluation board after powerup.

• The MICIN jack is self-shorting. Make sure

there is either something in the jack or that

the traces to the capacitors have been cut.

• When the 26dB gain stage is not in use, the

differential amplifier provided by U100

should be referenced around >2V, not VCM.

• Signal applied at FE_IN will come out of

SPKROUT. Signal applied at MICIN will

come out of FE_OUT.

• The signal applied at FE_IN should only be

picked up by MICIN from SPKROUT.

• Constant power signals (such as fixed ampli-

tude sine waves) will attenuate after several

seconds as the noise estimators determine

this signal to be noise.

Mode 1 hints:

• If the GPOUT1 LED is not lit after RESET,

the board is not operating properly. Make

sure the crystal is in the socket and make

sure it is oscillating. SCLK should be

2.048MHz.

• Make sure CONFIG is ON. Otherwise the

MC145480 is powered down.

• The default operation of the CS6403 will

force half-duplex mode upon powerup. Sev-

eral seconds of speech in both transmit and

receive directions will be necessary for full-

duplex operation.

Mode 2 hints:

• Make sure CONFIG is OFF. This powers

down the MC145480 and avoids contention

on SDI.

• Make sure SCLK and SSYNC are being re-

ceived.

46

DS192DB3

Share Link: