VP306SCG データシートの表示（PDF） - Mitel Networks

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VP306SCG

Satellite Channel Decoder

Mitel Networks 

VP305/6

DRAFT - PRELIMINARY DATA

1.3.1. Viterbi error count measurement.

A measure of the effectiveness of the Viterbi decoder in removing bit errors is provided in the

VP305/6. The incoming data bit stream is delayed and compared with the decoded bit stream to

obtain a count of errors corrected by the decoder, see the Fig. 7 below.

VITERBI

DECODER

DATA BIT STREAM

VITERBI

ENCODER

DELAY

COMP

ERROR COUNT

Fig. 7. Viterbi block diagram showing error count generation.

The measurement system has a programmable register to determine the number of data bits (the

error count period) over which the count is being recorded. A read register indicates the error

count result and an interrupt can be generated to inform the host microprocessor that a new count

is available.

The VIT ERR H-M-L group of three registers is programmed with required number of data bits (the

error count period) (VITEP[23:0]). The actual value is four times VITEP[23:0]. The count of errors

found during this period is loaded by the VP305/6 into the VIT ERR C H-L pair of registers when

the bit count VITEP[23:0] is reached. At the same time an interrupt is generated on the IRQ line.

The actual error count value is four times VERRC[15:0]. If a value of 65535 is read out, the error

count is too large for the VERRC[15:0] registers, so the error period in VITEP[23:0] should be

reduced. The interrupt is enabled by setting the IE_FEC[2] bit in the IE_FEC register, see

page 52. VERRC[15:0] is not cleared by reading the register, it is only loaded with the error count.

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

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