V436632S24VXTG-75PC データシートの表示（PDF） - Mosel Vitelic Corporation
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V436632S24VXTG-75PC
Mosel Vitelic Corporation
V436632S24VXTG-75PC Datasheet PDF : 12 Pages
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MOSEL VITELIC
V436632S24V
SPD-Table
Byte
Number
30
31
32
33
34
35
36-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Function Described
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
Reserved
Intel Specification for Frequency
Supported frequency
Unused Storage Location
SPD Entry Value
42 ns/45 ns
256 MByte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
Revision 2/1.2
Mosel Vitelic
V436632S24V
-75PC
2A
40
15
08
15
08
00
02
FD
40
00
Hex Value
-75
2D
40
15
08
15
08
00
02
42
40
00
-10PC
2D
40
20
10
20
10
00
12
B0
40
00
00
00
00
64
64
64
00
00
00
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage (IOUT = –4.0 mA)
VOL
Output Low Voltage (IOUT = 4.0 mA)
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < VCC)
Limit Values
Min.
Max.
2.0
–0.5
VCC+0.3
0.8
2.4
—
—
0.4
–10
10
–10
10
Unit
V
V
V
V
µA
µA
V436632S24V Rev. 1.0 January 2002
5
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