V436632S24VXTG-75PC HTML VIEW PDF DOWNLOAD, V436632S24VXTG-75PC データシート

V436632S24VXTG-75PC データシートの表示（PDF） - Mosel Vitelic Corporation

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V436632S24VXTG-75PC

3.3 VOLT 32M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SDRAM MODULE

Mosel Vitelic Corporation

V436632S24VXTG-75PC Datasheet PDF : 12 Pages

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MOSEL VITELIC

V436632S24V

Serial Presence Detect Information

A serial presence detect storage device –

E2PROM – is assembled onto the module. Informa-

tion about the module configuration, speed, etc. is

SPD-Table

written into the E2PROM device during module pro-

duction using a serial presence detect protocol (I2C

synchronous 2-wire bus)

Byte

Number

Function Described

SPD Entry Value

Number of SPD bytes

128

Total bytes in Serial PD

256

Memory Type

SDRAM

Number of Row Addresses (without BS bits)

Number of Column Addresses (for x8 SDRAM)

Number of DIMM Banks

Module Data Width

Module Data Width (continued)

Module Interface Levels

LVTTL

SDRAM Cycle Time at CL=3

7.5 ns/10.0 ns

SDRAM Access Time from Clock at CL=3

5.4 ns/6.0 ns

Dimm Config (Error Det/Corr.)

none

Refresh Rate/Type

Self-Refresh, 7.8µs

SDRAM width, Primary

Error Checking SDRAM Data Width

n/a / x8

Minimum Clock Delay from Back to Back Ran-

dom Column Address

tccd = 1 CLK

Burst Length Supported

1, 2, 4, 8

Number of SDRAM Banks

Supported CAS Latencies

CL = 2, 3

CS Latencies

CS Latency = 0

WE Latencies

WL = 0

SDRAM DIMM Module Attributes

Non Buffered/Non Reg.

SDRAM Device Attributes: General

Vcc tol ± 10%

Minimum Clock Cycle Time at CAS Latency = 2

7.5 ns /10.0 ns

Maximum Data Access Time from Clock for CL

5.4 ns/ 6.0 ns

Minimum Clock Cycle Time at CL = 1

Not Supported

Maximum Data Access Time from Clock at CL

Not Supported

Minimum Row Precharge Time

15 ns/20 ns

Minimum Row Active to Row Active Delay tRRD

Minimum RAS to CAS Delay tRCD

14 ns/15 ns/16 ns

15 ns/20 ns

-75PC

Hex Value

-75

-10PC

V436632S24V Rev. 1.0 January 2002

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