AS7C1024C データシートの表示（PDF） - Alliance Semiconductor
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AS7C1024C Datasheet PDF : 9 Pages
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AS7C1024C
®
Functional description
The AS7C1024C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high
performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank
systems.
When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB
power. If the bus is static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0
through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2).
To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE)
or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.
The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable
is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Vt1
Vt2
PD
Tstg
Tbias
IOUT
–0.50
–0.50
–
–55
–55
–
+7.0
V
VCC +0.50
V
1.25
W
+125
°C
+125
°C
50
mA
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE1
CE2
WE
OE
H
X
X
X
X
L
X
X
L
H
H
H
L
H
H
L
L
H
L
X
Key: X = don’t care, L = low, H = high.
Data
High Z
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1)
Standby (ISB, ISB1)
Output disable (ICC)
Read (ICC)
Write (ICC)
12/5/06, v. 1.0
Alliance Memory
P. 2 of 9
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