CY7C143-35JI データシートの表示（PDF） - Cypress Semiconductor

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CY7C143-35JI

2K x 16 Dual-Port Static RAM

Cypress Semiconductor 

CY7C133

CY7C143

Switching Waveforms

Read Cycle No.1 [21, 22]

Either Port Address Access

tRC

ADDRESS

tOHA

tAA

DATA OUT PREVIOUS DATA VALID

DATA VALID

Read Cycle No. 2 [21, 23]

CE

OE

DATA OUT

ICC

ISB

Either Port CE/OE Access

tACE

tLZOE

tLZCE

tDOE

tPU

tHZOE

DATA VALID

tHZCE

tPD

Read Cycle No. 3 [22]

ADDRESS R

R/WR

DINR

Read with BUSY (for master CY7C133)

tRC

ADDRESS MATCH

tPWE

tHD

VALID

ADDRESS L

BUSYL

DOUTL

tPS

tBLA

Note:

21. R/W is HIGH for read cycle.

22. Device is continuously selected, CE = VIL and OE = VIL.

23. Address valid prior to or coincidence with CE transition LOW.

ADDRESS MATCH

tBHA

tWDD

tDDD

tBDD

VALID

Document #: 38-06036 Rev. *B

Page 8 of 13

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