CY7C143-35JI データシートの表示（PDF） - Cypress Semiconductor
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CY7C143-35JI Datasheet PDF : 13 Pages
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CY7C133
CY7C143
Table 1. Non-Contending Read/Write Control
Control
R/WLB R/WUB
CE
OE
X
X
H
X
L
L
L
X
L
H
L
L
H
L
L
L
L
H
L
H
H
L
L
H
H
H
L
L
H
H
L
H
I/O
I/O0–I/O8
High Z
I/O9–I/O17
High Z
Data In
Data In
Data In
Data Out
Data Out
Data In
Data In
High Z
High Z
Data In
Data Out
Data Out
High Z
High Z
Operation
Deselected: Power-Down
Write to Both Bytes
Write Lower Byte, Read Upper Byte
Read Lower Byte, Write Upper Byte
Write to Lower Byte
Write to Upper Byte
Read to Both Bytes
High Impedance Outputs
Table 2. Address BUSY Arbitration
Inputs
CEL
CER
X
X
AddressL
AddressR
No Match
H
X
Match
X
H
Match
L
L
Match
Outputs
BUSYL
H
H
H
Note 3
BUSYR
H
H
H
Note 3
Function
Normal
Normal
Normal
Write Inhibit[4]
32-Bit Master/Slave Dual-Port Memory Systems
R/W
BUSY
LEFT
CY7C133
RIGHT
R/W
BUSY
5V
5V
R/W
BUSY
CY7C143
R/W
BUSY
Table 3. Arbitration Results
Port
Case
Left
Right
Winning Port
Result
1
Read
Read
L
Both ports read
2
Read
Read
R
Both ports read
3
Read
Write
L
L port reads OK R port write inhibited
4
Read
Write
R
R port writes OK L port data may be invalid
5
Write
Read
L
L port writes OK R port data may be invalid
6
Write
Read
R
R port reads OK L port write inhibited
7
Write
Write
L
L port writes OK R port write inhibited
8
Write
Write
R
R port writes OK L port write inhibited
Notes:
3. The loser of the port arbitration will receive BUSY = “L” (BUSYL or BUSYR = “L”). BUSYL and BUSYR cannot both be LOW simultaneously.
4. Writes are inhibited to the left port when BUSYL is LOW. Writes are inhibited to the right port when BUSYR is LOW.
Document #: 38-06036 Rev. *B
Page 4 of 13
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