AN-9050 データシートの表示（PDF） - Fairchild Semiconductor

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AN-9050

FDMF6704 Power Loss Calculation

Fairchild Semiconductor 

APP NOTE NUMBER

error between calculated result with datasheet graphs and

real lab data from test.

Calculated

Module Ploss

Real

Module Ploss

Ploss Error

7.921 W

7.96 W

(1-7.921/7.96)*100

=0.495 %

Table 5. Power Loss Error of Example 1

APPLICATION NOTE

z Example 2

1. Define design parameters

Vin=10 V

Vcin & Vdrv=5.5 V

Vout=2 V

Iout=25 A

Fsw=600 kHz

Inductor=320 nH

2. Calculate each steps

- Find reference design parameter values and

module power loss with Figure 3 Æ 4.6 W with 12

Vin, 5 Vcin, 1.3 Vout, 25 A, 350 kHz and 440 nH

- Ploss at 10 Vin. Note Figure 6:

4.6 W * 1.016 = 4.674 W

- Ploss at 10 Vin and 5.5 Vcin. Note Figure 7

4.674 W * 0.957 = 4.473 W

- Ploss at 10 Vin, 5.5 Vcin and 2 Vout. Note Figure

4:

4.473 W * 1.13 = 5.054 W

- Ploss at 10 Vin, 5.5 Vcin, 2 Vout and 600 kHz.

Note Figure 5:

5.054 W * 1.12 = 5.661 W

- Ploss at 10 Vin, 5.5 Vcin, 2 Vout, 600 kHz and

320 nH. Note Figure 8:

5.661 W * 1.007 = 5.7 W

- The calculated module power loss is 5.7 W. The

error between calculated and real data is around

3.8 %. See Table 6 below for error calculation.

Calculated

Module Ploss

Real

Module Ploss

Ploss Error

5.7 W

5.489 W

(1-5.7/5.489)*100

=-3.844 %

Table 6. Power Loss Error of Example 2

© 2007 Fairchild Semiconductor Corporation

Rev. 1.0.0 • 7/14/09

4

Figure 6. Normalized Module Ploss vs. Vin

Figure 7. Normalized Module Ploss vs. Vcin&Vdrv

Figure 8. Normalized Module Ploss vs. Lout

www.fairchildsemi.com

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