EBD21RD4ABNA-10 データシートの表示（PDF） - Elpida Memory, Inc

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EBD21RD4ABNA-10

2GB Registered DDR SDRAM DIMM

Elpida Memory, Inc 

EBD21RD4ABNA

13. tDAL = (tWR/tCK)+(tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,

tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)

tDAL = 5 clocks

Timing Parameter Measured in Clock Cycle for Registered DIMM

Parameter

Write to pre-charge command delay (same bank)

Read to pre-charge command delay (same bank)

Write to read command delay (to input all data)

Burst stop command to write command delay

(CL = 3)

(CL = 3.5)

Burst stop command to DQ High-Z

(CL = 3)

(CL = 3.5)

Read command to write command delay (to output all data)

(CL = 3)

(CL = 3.5)

Pre-charge command to High-Z

(CL = 3)

(CL = 3.5)

Write command to data in latency

Write recovery

Register set command to active or register set command

Self refresh exit to non-read command

Self refresh exit to read command

Power down entry

Power down exit to command input

Symbol

tWPD

tRPD

tWRD

tBSTW

tBSTW

tBSTZ

tBSTZ

tRWD

tRWD

tHZP

tHZP

tWCD

tWR

tMRD

tSNR

tSRD

tPDEN

tPDEX

Number of clock cycle

min.

max.

3 + BL/2

BL/2

2 + BL/2

2

3

3

3

3.5

3.5

2 + BL/2

3 + BL/2

3

3

3.5

3.5

2

2

1

2

10

200

1

1

1

Preliminary Data Sheet E0273E20 (Ver. 2.0)

14

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