AIC1341 データシートの表示（PDF） - Analog Intergrations

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AIC1341

High Performance, Triple-Output, Auto-Tracking Combo Controller

Analog Intergrations 

n DESCRIPTION

The AIC1341 is designed for applications with

multiple voltage demand. This IC has one PWM

controller and two linear controllers. The PWM

controller is designed to regulate the voltage

(VOUT1) by driving 2 MOSFETs (B y UGATE and

LGATE) in a synchronous rectified buck converter

configuration. The voltage is regulated to a level,

which is decided by a resistor devide network.

The Power-On Reset (POR) function continually

monitors the input supply voltage +12V at VCC

pin, the 5V input voltage at OCSET pin, and the

3.3V input at VIN2 pin. The POR function initiates

soft-start operation after all three input supply

voltage exceeds their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence.

Initially, the voltage on SS pin rapidly increases to

approximate 1V. Then an internal 10µA current

source charges an external capacitor (CSS) on the

SS pin to 4V. As the SS pin voltage slews from

1V to 4V, the PWM error amplifier reference input

(Non-inverting terminal) and output (COMP1 pin) is

clamped to a level proportional to the SS pin volt-

age. As the SS pin voltage slew from 1V to 4V,

the output clamp generates PHASE pulses of in-

creasing width that charge the output capacitors.

Additionally both linear regulator’s reference in-

puts are clamped to a voltage proportional to the

SS pin voltage. This method provides a controlled

output voltage smooth rise.

Fig.3 shows the soft-start sequence for the typical

application. The internal oscillator’s triangular

waveform is compared to the clamped error ampli-

fier output voltage. As the SS pin voltage in-

creases, the pulse width on PHASE pin increases.

The interval of increasing pulse width continues

until output reaches sufficient voltage to transfer

control to the input reference clamp.

Each linear output (VOUT2 and VOUT3) initially

follows a ramp. When each output reaches suffi-

AIC1341

cient voltage the input reference clamp slows the

rate of output voltage rise.

Over-Current Protection

All outputs are protected against excessive over-

current. The PWM controller uses upper

MOSFET’s on-resistance, RDS(ON) to monitor the

current for protection against shorted outputs.

Both the linear regulator and controller monitor

FB2 and FB3 for under-voltage to protect against

excessive current.

When the voltage across Q1 (ID• RDS(ON)) ex-

ceeds the level (200µA•ROCSET), this signal in-

hibit all outputs. Discharge soft-start capacitor

(Css) with 10µA current sink, and increments the

counter. Css recharges and initiates a soft-start

cycle again until the counter increments to 3. This

sets the fault latch to disable all outputs. Fig. 2

illustrates the over-current protection until an over

load on OUT1.

Should excessive current cause FB2 or FB3 to fall

below the linear under-voltage threshold, the LUV

signal sets the over-current latch if Css is fully

charged. Cycling the bias input power off then on

reset the counter and the fault latch.

The over-current function for PWM controller will

trip at a peak inductor current (IPEAK) determined

by:

IPEAK = IOCSET × ROCSET

RDS(ON)

The OC trip point varies with MOSFET’s tempera-

ture. To avoid over-current tripping in the normal

operating load range, determine the ROCSET resis-

tor from the equation above with:

1. The maximum RDS(ON) at the highest junction.

2. The minimum IOCSET from the specification table.

3. Determine IPEAK > IOUT(MAX) + (inductor ripple

current) /2.

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