AIC1341 データシートの表示（PDF） - Analog Intergrations
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AIC1341 Datasheet PDF : 14 Pages
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IRIPPLE = (VIN − VOUT) × VOUT ;
f × L × VIN
f = 200KHz oscillator frequency.
The inductor must be able to withstand peak cur-
rent without saturation, and the copper resistance
in the winding should be kept as low as possible
to minimize resistive power loss
Input Capacitor Selection
Most of the input supply current is supplied by the
input bypass capacitor, the resulting RMS current
flow in the input capacitor will heat it up. Use a
mix of input bulk capacitors to control the voltage
overshoot across the upper MOSFET. The ce-
ramic capacitance for the high frequency decou-
pling should be placed very close to the upper
MOSFET to suppress the voltage induced in the
parasitic circuit impedance. The buck capacitors
to supply the RMS current is approximate equal
to:
IRMS = (1− D) ×
D×
I2 OUT
+
1
12
×
VfIN××LD
2
, where D = VOUT
VIN
The capacitor voltage rating should be at least
1.25 times greater than the maximum input volt-
age.
PWM MOSFET Selection
In high current PWM application, the MOSFET
power dissipation, package type and heatsink are
the dominant design factors. The conduction loss
is the only component of power dissipation for the
lower MOSFET, since it turns on into near zero
voltage. The upper MOSFET has conduction loss
and switching loss. The gate charge losses are
proportional to the switching frequency and are
AIC1341
dissipated by the AIC1341. However, the gate
charge increases the switching interval, tSW, which
increase the upper MOSFET switching losses.
Ensure that both MOSFETs are within their
maximum junction temperature at high ambient
temperature by calculating the temperature rise
according to package thermal resistance specifi-
cations.
PUPPER = IOUT2 × RDS(ON) × D + IOUT × VIN × tSW × f
2
PLOWER = IOUT2 × RDS(ON) × (1− D)
The equations above do not model power loss due
to the reverse recovery of the lower MOSFET’s
body diode.
The RDS(ON) is different for the two previous equa-
tions even if the type devices is used for both.
This is because the gate drive applied to the upper
MOSFET is different than the lower MOSFET.
Logic level MOSFETs should be selected based
on on-resistance considerations, RDS(ON) should
be chosen base on input and output voltage, al-
lowable power dissipation and maximum required
output current. Power dissipation should be cal-
culated based primarily on required efficiency or
allowable thermal dissipation.
Rectifier Schottky diode is a clamp that prevent
the loss parasitic MOSFET body diode from con-
ducting during the dead time between the turn off
of the lower MOSFET and the turn on of the upper
MOSFET. The diode’s rated reverse breakdown
voltage must be greater than twice the maximum
input voltage.
Linear Controller MOSFET Selection
The power dissipated in a linear regulator is :
PLINEAR = IOUT × (VIN2 − VOUT)
Select a package and heatsink that maintains
junction temperature below the maximum rating
11
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