ADSP-2195MKCA-160X データシートの表示（PDF） - Analog Devices

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ADSP-2195MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

ADSP-2195

For current information contact Analog Devices at 800/262-5643

September 2001

JTAG Emulator Pod Connector

Figure 9 details the dimensions of the JTAG pod connector

at the 14-pin target end. Figure 10 displays the keep-out

area for a target board header. The keep-out area allows the

pod connector to properly seat onto the target board header.

This board area should contain no components (chips,

resistors, capacitors, etc.). The dimensions are referenced

to the center of the 0.25" square post pin.

Design-for-Emulation Circuit Information

For details on target board design issues including: single

processor connections, multiprocessor scan chains, signal

buffering, signal termination, and emulator pod logic, see

the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.ana-

log.com)—use site search on “EE-68”. This document is

updated regularly to keep pace with improvements to

emulator support.







Figure 9. JTAG Pod Connector Dimensions





Figure 10. JTAG Pod Connector Keep-Out Area

Additional Information

This data sheet provides a general overview of the

ADSP-2195 architecture and functionality. For detailed

information on the ADSP-219x family core architecture

and instruction set, refer to the ADSP-219x/2191 DSP

Hardware Reference.

PIN DESCRIPTIONS

ADSP-2195 pin definitions are listed in Table 7. All

ADSP-2195 inputs are asynchronous and can be asserted

asynchronously to CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDDEXT or GND,

except for ADDR21–0, DATA15–0, PF7-0, and inputs that

have internal pull-up or pull-down resistors (TRST,

BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS,

TDI, and RESET)—these pins can be left floating. These

pins have a logic-level hold circuit that prevents input from

floating internally.

The following symbols appear in the Type column of

Table 7: G = Ground, I = Input, O = Output, P = Power

Supply, and T = Three-State.

Table 7. Pin Descriptions

Pin

A21–0

D7–0

D15

/PF15

/SPI1SEL7

D14

/PF14

/SPI0SEL7

D13

/PF12

/SPI1SEL6

D12

/PF12

/SPI0SEL6

Type Function

O/T External Port Address Bus

I/O/T External Port Data Bus, least significant 8 bits

I/O/T Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave

I/O Select output 7 (if 8-bit external bus, when SPI1 enabled)

I

I/O/T Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave

I/O Select output 7 (if 8-bit external bus, when SPI0 enabled)

I

I/O/T Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave

I/O Select output 6 (if 8-bit external bus, when SPI1 enabled)

I

I/O/T Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave

I/O Select output 6 (if 8-bit external bus, when SPI0 enabled)

I

18

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrA

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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