ADSP-2195MKCA-160X データシートの表示（PDF） - Analog Devices

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ADSP-2195MKCA-160X

DSP Microcomputer

Analog Devices 

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ADSP-2195

For current information contact Analog Devices at 800/262-5643

September 2001

To exit Power-Down Core/Peripherals mode, the DSP

responds to an interrupt and (after 500 cycles to re-stabilize

the PLL) resumes executing instructions with the instruc-

tion after the IDLE.

Clock Signals

The ADSP-2195 can be clocked by a crystal oscillator or a

buffered, shaped clock derived from an external clock oscil-

lator. If a crystal oscillator is used, the crystal should be

connected across the CLKIN and XTAL pins, with two

capacitors connected as shown in Figure 6. Capacitor

values are dependent on crystal type and should be specified

by the crystal manufacturer. A parallel-resonant, funda-

mental frequency, microprocessor-grade crystal should be

used for this configuration.

If a buffered, shaped clock is used, this external clock

connects to the DSP’s CLKIN pin. CLKIN input cannot

be halted, changed, or operated below the specified

frequency during normal operation. This clock signal

should be a TTL-compatible signal. When an external clock

is used, the XTAL input must be left unconnected.

The DSP provides a user-programmable 1؋ to 32؋ multi-

plication of the input clock, including some fractional

values, to support 128 external to internal (DSP core) clock

ratios. The MSEL6–0, BYPASS, and DF pins decide the

PLL multiplication factor at reset. At runtime, the multipli-

cation factor can be controlled in software. To support input

clocks greater that 100 MHz, the PLL uses an additional

input: the Divide Frequency (DF) pin. If the input clock is

greater than 100 MHz, DF must be high. If the input clock

is less than 100 MHz, DF must be low. The combination of

pullup and pull-down resistors in Figure 6 set up a core

clock ratio of 6:1, which produces a 150 MHz core clock

from the 25 MHz input. For other clock multiplier settings,

see the ADSP-219x/2191 DSP Hardware Reference.

The peripheral clock is supplied to the CLKOUT pin.

All on-chip peripherals for the ADSP-2195 operate at the

rate set by the peripheral clock. The peripheral clock is

either equal to the core clock rate or one-half the DSP core

clock rate. This selection is controlled by the IOSEL bit in

the PLLCTL register. The maximum core clock

is 160 MHz, and the maximum peripheral clock

is 100 MHz—the combination of the input clock and

core/peripheral clock ratios may not exceed these limits.

Reset

The RESET signal initiates a master reset of the

ADSP-2195. The RESET signal must be asserted during

the power-up sequence to assure proper initialization.

RESET during initial power-up must be held long enough

to allow the internal clock to stabilize. If RESET is activated

any time after power up, the clock does not continue to run

and requires stabilization time when recovering from reset.

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Figure 6. External Crystal Connections

The power-up sequence is defined as the total time required

for the crystal oscillator circuit to stabilize after a valid VDD

is applied to the processor, and for the internal phase-locked

loop (PLL) to lock onto the specific crystal frequency. A

minimum of 100 µs ensures that the PLL has locked, but

does not include the crystal oscillator start-up time. During

this power-up sequence the RESET signal should be held

low. On any subsequent resets, the RESET signal must meet

the minimum pulsewidth specification, tRSP.

The RESET input contains some hysteresis. If using an RC

circuit to generate your RESET signal, the circuit should

use an external Schmidt trigger.

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts, and resets all registers

to their default values (where applicable). When RESET is

released, if there is no pending bus request and the chip is

configured for booting, the boot-loading sequence is per-

formed. Program control jumps to the location of the

on-chip boot ROM (0xFF0000).

Power Supplies

The ADSP-2195 has separate power supply connections for

the internal (VDDINT) and external (VDDEXT) power supplies.

The internal supply must meet the 2.5 V requirement. The

external supply must be connected to a 3.3 V supply. All

external supply pins must be connected to the same supply.

14

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrA

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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