ADSP-2184NKCA-320 データシートの表示（PDF） - Analog Devices

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ADSP-2184NKCA-320

DSP Microcomputer

Analog Devices 

ADSP-218xN Series

Interrupts

The interrupt controller allows the processor to respond to

the eleven possible interrupts and reset with minimum over-

head. ADSP-218xN series members provide four dedicated

external interrupt input pins: IRQ2, IRQL0, IRQL1, and

IRQE (shared with the PF7–4 pins). In addition, SPORT1

may be reconfigured for IRQ0, IRQ1, FI and FO, for a total

of six external interrupts. The ADSP-218xN also supports

internal interrupts from the timer, the byte DMA port, the

two serial ports, software, and the power-down control cir-

cuit. The interrupt levels are internally prioritized and indi-

vidually maskable (except power-down and reset). The

IRQ2, IRQ0, and IRQ1 input pins can be programmed to

be either level- or edge-sensitive. IRQL0 and IRQL1 are

level-sensitive and IRQE is edge-sensitive. The priorities

and vector addresses of all interrupts are shown in Table 6.

Table 6. Interrupt Priority and Interrupt Vector

Addresses

Source Of Interrupt

Reset (or Power-Up with

PUCR = 1)

Power-Down

(Nonmaskable)

IRQ2

IRQL1

IRQL0

SPORT0 Transmit

SPORT0 Receive

IRQE

BDMA Interrupt

SPORT1 Transmit or

IRQ1

SPORT1 Receive or IRQ0

Timer

Interrupt Vector Address

(Hex)

0x0000 (Highest Priority)

0x002C

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially. In-

terrupts can be masked or unmasked with the IMASK reg-

ister. Individual interrupt requests are logically ANDed

with the bits in IMASK; the highest priority unmasked in-

terrupt is then selected. The power-down interrupt is non-

maskable.

ADSP-218xN series members mask all interrupts for one

instruction cycle following the execution of an instruction

that modifies the IMASK register. This does not affect serial

port autobuffering or DMA transfers.

The interrupt control register, ICNTL, controls interrupt

nesting and defines the IRQ0, IRQ1, and IRQ2 external

interrupts to be either edge- or level-sensitive. The IRQE

pin is an external edge-sensitive interrupt and can be forced

and cleared. The IRQL0 and IRQL1 pins are external level

sensitive interrupts.

The IFC register is a write-only register used to force and

clear interrupts. On-chip stacks preserve the processor

status and are automatically maintained during interrupt

handling. The stacks are 12 levels deep to allow interrupt,

loop, and subroutine nesting. The following instructions

allow global enable or disable servicing of the interrupts

(including power-down), regardless of the state of IMASK:

ENA INTS;

DIS INTS;

Disabling the interrupts does not affect serial port auto-

buffering or DMA. When the processor is reset, interrupt

servicing is enabled.

LOW-POWER OPERATION

ADSP-218xN series members have three low-power modes

that significantly reduce the power dissipation when the

device operates under standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Power-Down

ADSP-218xN series members have a low-power feature that

lets the processor enter a very low-power dormant state

through hardware or software control. Following is a brief

list of power-down features. Refer to the ADSP-218x DSP

Hardware Reference, “System Interface” chapter, for detailed

information about the power-down feature.

• Quick recovery from power-down. The processor begins

executing instructions in as few as 200 CLKIN cycles.

• Support for an externally generated TTL or CMOS

processor clock. The external clock can continue running

during power-down without affecting the lowest power

rating and 200 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscil-

lator to save power (the processor automatically waits

approximately 4096 CLKIN cycles for the crystal oscilla-

tor to start or stabilize), and letting the oscillator run to

allow 200 CLKIN cycle start-up.

• Power-down is initiated by either the power-down pin

(PWD) or the software power-down force bit. Interrupt

support allows an unlimited number of instructions to be

executed before optionally powering down. The power-

down interrupt also can be used as a nonmaskable, edge-

sensitive interrupt.

• Context clear/save control allows the processor to

continue where it left off or start with a clean context when

leaving the power-down state.

–8–

REV. 0

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