ADSP-21261 データシートの表示（PDF） - Analog Devices

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ADSP-21261

SHARC Embedded Processor

Analog Devices 

ADSP-21261/ADSP-21262/ADSP-21266

Timer WDTH_CAP Timing

The timing specification in Table 21 and Figure 12 applies to

Timer in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 21. Timer Width Capture Timing

Parameter

Timing Requirements

tPWI

Timer Pulse Width

Min

2 × tCCLK

Max

2(231 – 1) × tCCLK

Unit

ns

TIMER

CAPTURE

INPUTS

tPWI

Figure 12. Timer Width Capture Timing

DAI Pin-to-Pin Direct Routing

See Table 22 and Figure 13 for direct pin connections only (for

example, DAI_PB01_I to DAI_PB02_O).

Table 22. DAI Pin-to-Pin Routing

Parameter

Timing Requirements

tDPIO

Delay DAI Pin Input Valid to DAI Output Valid

Min

Max

Unit

1.5

10

ns

DAI_Pn

DAI_Pm

tDPIO

Figure 13. DAI Pin-to-Pin Direct Routing

Rev. G | Page 21 of 48 | December 2012

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