ADL5570-EVALZ データシートの表示（PDF） - Analog Devices
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ADL5570-EVALZ Datasheet PDF : 12 Pages
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ADL5570
APPLICATIONS
BASIC CONNECTIONS
Figure 10 shows the basic connections for the ADL5570.
STBY
VPOS
L1
C6
C11
C8
1nH
3.6pF
1µF
VPOS
0.01µF
VPOS1
C7
0.01µF
L2
11nH
C5
C12
OPEN
1µF
RFIN L3
2.7nH
VREG
C9
0.01µF
5 VCC1
NC 16
6 RFIN
7 GND
RFOUT 15
ADL5570
RFOUT 14
8 VREG
NC 13
C3
3.3pF
C4 RFOUT
39pF
C2
2.2pF
VPOS1
W1
R1
50kΩ
C10
0.01µF
MODE
VPOS
NC = NO CONNECT
Figure 10. ADL5570 Basic Connections
Power Supply
The voltage supply on the ADL5570, which ranges from
3.2 V to 4.2 V, should be connected to the VCCx pins. VCC1 is
decoupled with Capacitor C7, whereas VCC2 uses a tank circuit
to prevent RF signals from propagating on the dc lines.
RF Input Interface
The RFIN pin is the port for the RF input signal to the
power amplifier. The L3 inductor, 2.7 nH, matches the input
impedance to 50 Ω.
2.7nH
L3
6 RFIN
Figure 11. RF Input with Matching Component
RF Output Interface
The parallel RF output ports have a shunt capacitance, C3 (3.3 pF),
and the line inductance of the microstrip-line for optimized
output power and linearity. The characteristics of the ADL5570
are described for 50 Ω impedance after the output matching
capacitor (load after C3).
VPOS1
L2
11pF
C5
C12
OPEN 1µF
RFOUT 15
RFOUT 14
C4
39pF
C3
3.3pF
RFOUT
Figure 12. RF Output
C4 provides dc blocking on the RF output.
Transmit/Standby Enable
During normal transmit mode, the STBY pin is biased low
(0 V). However, during receive mode, the pin can be biased
high (2.5 V) to shift the device into standby mode, which
reduces current consumption to less than 1 mA.
VREG Enable
During normal transmit, the VREG pin is biased to 2.85 V and
draws 10 mA of current. When the VREG pin is low (0 V), the
device suspends itself into sleep mode (irrespective of supply
and MODE biasing). In this mode, the device draws 10 μA of
current.
MODE High Power/Low Power Enable
The MODE pin is used to choose between high power mode
and low power mode. When MODE is biased low (0 V), the
device operates in high power mode. When MODE is biased
high (2.5 V), the device operates in low power mode. Appropriate
biasing must be followed for 3.5 V and 4.2 V operation. See
Table 4 and Table 5 for configuration of the MODE pin.
Rev. 0 | Page 8 of 12
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