ADG823(Rev0) データシートの表示（PDF） - Analog Devices
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ADG823 Datasheet PDF : 12 Pages
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PIN CONFIGURATION
8-Lead MSOP
(RM-8)
ADG821/ADG822/ADG823
S1 1 TOP VIEW 8 VDD
D1 2 (Not to Scale) 7 IN1
IN2 3
GND 4
ADG821/
ADG822/
ADG823
6 D2
5 S2
VDD
GND
IDD
S
D
IN
RON
∆RON
RFLAT(ON)
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
VINL
VINH
IINL (IINH)
CS (OFF)
CD (OFF)
CD, CS (ON)
tON
tOFF
tBBM
Charge Injection
Crosstalk
Off Isolation
Bandwidth
On Response
Insertion Loss
TERMINOLOGY
Most Positive Power Supply Potential
Ground (0 V) Reference
Positive Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Ohmic Resistance between D and S
On Resistance Match between any Two Channels (i.e., RON max – RON min)
Flatness is defined as the difference between the maximum and minimum value of on resistance as
measured over the specified analog signal range.
Source Leakage Current with the Switch OFF
Drain Leakage Current with the Switch OFF
Channel Leakage Current with the Switch ON
Analog Voltage on Terminals D and S
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
OFF Switch Source Capacitance
OFF Switch Drain Capacitance
ON Switch Capacitance
Delay between Applying the Digital Control Input and the Output Switching ON
Delay between Applying the Digital Control Input and the Output Switching OFF
OFF time or ON time measured between the 90% points of both switches, when switching from one
address state to another.
It is a measure of the glitch impulse transferred from the digital input to the analog output during switching.
It is a measure of unwanted signal that is coupled through from one channel to another as a result
of parasitic capacitance.
A Measure of Unwanted Signal Coupling through an OFF Switch
The Frequency at which the Output Is Attenuated by –3 dBs
The Frequency Response of the ON Switch
The Loss due to the On Resistance of the Switch
REV. 0
–5–
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