ADG725 データシートの表示（PDF） - Analog Devices
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ADG725 Datasheet PDF : 16 Pages
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TIMING CHARACTERISTICS1, 2
ADG725/ADG731
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
30
t1
33
t2
13
t3
13
t4
13
t5
40
t6
5
t7
4.5
t8
33
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Minimum SYNC Low Time
Data Setup Time
Data Hold Time
Minimum SYNC High Time
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
SCLK
SYNC
DIN
t8 t4
t5
t7
t6
DB7
t1
t2
t3
DB0
Figure 1. 3-Wire Serial Interface Timing Diagram
DB7 (MSB)
EN CSA CSB X
DB0 (LSB)
A3 A2 A1 A0
DATA BITS
Figure 2. ADG725 Input Shift Register Contents
DB7 (MSB)
DB0 (LSB)
EN CS X A4 A3 A2 A1 A0
DATA BITS
Figure 3. ADG731 Input Shift Register Contents
REV. A
–5–
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