AD5764(RevPrC) データシートの表示（PDF） - Analog Devices

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AD5764
(Rev.:RevPrC)

Complete, Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC

Analog Devices 

Preliminary Technical Data

AD5764

DATA REGISTER

The Data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 7). The 16 data bits are in positions D15 to D0 as shown in Table 10.

Table 10. Programming the Data Register

REG2 REG1 REG0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

1

0 DAC Address

16 Bit DAC Data

COARSE GAIN REGISTER

The Coarse Gain Register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC Channel the

Data transfer is to take place (Refer to Table 7). The Coarse Gain Register ia a 2-bit register and allows the user to select the output range

of each DAC as shown in Table 12.

Table 11. Programming the Coarse Gain Register

REG2 REG1 REG0 A2 A1 A0 D15 …. D2 D1 D0

0

1

1 DAC Address Don’t Care CG1 CG0

Table 12. Output Range Selection

Output Range CG1 CG0

± 10 V

± 10.25 V

± 10.5 V

0

0

0

1

1

0

FINE GAIN REGISTER

The Fine Gain Register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 7). The Fine Gain Register is a 6-bit register and allows the user to adjust the gain of each DAC

channel by -32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 13 and Table 14.

Table 13. Programming the Fine Gain Register

REG2 REG1 REG0 A2 A1 A0

1

0

0 DAC Address

D15 …. D6 D5 D4 D3 D2 D1 D0

Don’t Care FG5 FG4 FG3 FG2 FG1 FG0

Table 14. Fine Gain Register Options

Gain Adjustment

+31 LSBs

+30 LSBs

No Adjustment

-31 LSBs

-32 LSBs

FG5 FG4 FG3 FG2 FG1 FG0

000000

000001

-

-

-

-

-

-

100000

-

-

-

-

-

-

111110

111111

Rev. PrC 21-Oct-04| Page 21 of 28

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