AD1940(Rev0) データシートの表示（PDF） - Analog Devices
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AD1940 Datasheet PDF : 32 Pages
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AD1940
DIGITAL TIMING
Table 5 Digital Timing1
Parameter
tMP
MCLK Period
tMP
MCLK Period
tMP
MCLK Period
tMP
MCLK Period
tMP
MCLK Period
tMDC
MCLK Duty Cycle
tBIL
BCLK_IN LO Pulse Width
tBIH
BCLK_IN HI Pulse Width
tLIS
LRCLK_IN Setup
tLIH
LRCLK_IN Hold
tSIS
SDATA_INx Setup
tSIH
SDATA_INx Hold
tLOS
LRCLK_OUTx Setup
tLOH
LRCLK_OUTx Hold
tTS
BCLK_OUTx Falling to
LRCLK_OUTx Timing Skew
tSODS
SDATA_OUTx Delay
tSODM
SDATA_OUTx Delay
tCCPL
CCLK Pulse Width LO
tCCPH
CCLK Pulse Width HI
tCLS
CLATCH Setup
tCLH
CLATCH Hold
tCLPH
CLATCH Pulse Width HI
tCDS
CDATA Setup
tCDH
CDATA Hold
tCOD
COUT Delay
tRLPW
RESETB LO Pulse Width
Comments
512 fS mode
384 fS mode
256 fS mode
64 fS mode
Bypass mode
Bypass mode
To BCLK_IN rising
From BCLK_IN rising
To BCLK_IN rising
From BCLK_IN rising
Slave mode
Slave mode
Slave mode, from BCLK_OUTx falling
Master mode, from BCLK_OUTx falling
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
From CCLK rising
Min
36
48
73
291
12
40
4
2
12
0
3
2
2
2
1 × INTMCLK (14)2
1 × INTMCLK (14)2
0
2 × INTMCLK + 4 (32)2
2 × INTMCLK (28)2
0
2 × INTMCLK + 2 (30)2
10
Max
Unit
244
ns
366
ns
488
ns
1953
ns
ns
60
%
ns
ns
ns
ns
ns
ns
ns
ns
2
ns
17
ns
17
ns
ns
ns
ns
ns
ns
ns
ns
4 × INTMCLK +18 (74)2 ns
ns
1 All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 32.
2 These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 × fs, so the internal master
clock at fs = 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.
PLL
Table 6.
Parameter
Lock Time
Min
Typ
Max
Unit
3
20
ms
REGULATOR
Table 7.
Parameter
VSENSE Output Voltage
Min
Typ
Max
Unit
2.25
2.5
2.68
V
Rev. 0 | Page 4 of 32
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