28F128 データシートの表示（PDF） - Intel
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28F128 Datasheet PDF : 58 Pages
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28F128J3A, 28F640J3A, 28F320J3A
Table 3. Bus Operations
Mode
Notes RP#
Read Array
Output Disable
Standby
Reset/Power-Down
Mode
Read Identifier Codes
4,5,6 VIH
VIH
VIH
VIL
VIH
Read Query
VIH
Read Status (WSM off)
VIH
Read Status (WSM on)
VIH
Write
6,10,11 VIH
CE0,1,2(1)
Enabled
Enabled
Disabled
X
Enabled
Enabled
Enabled
Enabled
Enabled
OE#(2)
VIL
VIH
X
X
VIL
VIL
VIL
VIL
VIH
WE#(2)
VIH
VIH
X
X
VIH
VIH
VIH
VIH
VIL
Address VPEN
X
X
X
X
X
X
X
X
DQ(3)
DOUT
High Z
High Z
High Z
STS
(default
mode)
High Z(7)
X
X
High Z(7)
See
Figure 5
See
Table 7
X
X
X
X
Note 8
X
Note 9
X
X
VPENH
DOUT
DQ7 = DOUT
DQ15–8 = High Z
DQ6–0 = High Z
DIN
High Z(7)
High Z(7)
X
NOTES:
1. See Table 2 for valid CE configurations.
2. OE# and WE# should never be enabled simultaneously.
3. DQ refers to DQ0–DQ7 if BYTE# is low and DQ0–DQ15 if BYTE# is high.
4. Refer to DC Characteristics. When VPEN ≤ VPENLK, memory contents can be read, but not altered.
5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for
VPENLK and VPENH voltages.
6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit
configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with
programming inactive), program suspend mode, or reset/power-down mode.
7. High Z will be VOH with an external pull-up resistor.
8. See Section 3.6 for read identifier code data.
9. See Section 4.2 for read query data.
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN =
VPENH and VCC is within specification.
11. Refer to Table 4 for valid DIN during a write operation.
Preliminary
11
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