28F128 データシートの表示（PDF） - Intel
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28F128 Datasheet PDF : 58 Pages
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28F128J3A, 28F640J3A, 28F320J3A
3.1
Read
Information can be read from any block, query, identifier codes, or status register independent of
the VPEN voltage.
Upon initial device power-up or after exit from reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read
Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data
flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be
enabled (see Table 2, “Chip Enable Truth Table” on page 7), and OE# must be driven active to
obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled
(see Table 2), select the memory device. OE# is the data output (DQ0–DQ15) control and, when
active, drives the selected memory data onto the I/O bus. WE# must be at VIH.
When reading information in read array mode, the device defaults to asynchronous page mode.
This mode provides high data transfer rate for memory subsystems. In this state, data is internally
read and stored in a high-speed page buffer. A2:0 addresses data in the page buffer. The page size is
four words or eight bytes. Asynchronous word/byte mode is supported with no additional
commands required.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.3
Standby
CE0, CE1, and CE2 can disable the device (see Table 2) and place it in standby mode which
substantially reduces device power consumption. DQ0–DQ15 outputs are placed in a high-
impedance state independent of OE#. If deselected during block erase, program, or lock-bit
configuration, the WSM continues functioning, and consuming active power until the operation
completes.
3.4
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and status register is
set to 80H.
During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the
reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.
8
Preliminary
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