MC100EL34DR2(2000) データシートの表示（PDF） - ON Semiconductor

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MC100EL34DR2
(Rev.:2000)

5V ECL ÷2, ÷4, ÷8 Clock Generation Chip

ON Semiconductor 

MC10EL34, MC100EL34

Driver

Device

Q

Qb

50 W

D

Receiver

Device

Db

50 W

V TT

V TT = V CC – 2.0 V

Figure 2. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 – Termination of ECL Logic Devices.)

Resource Reference of Application Notes

AN1404

– ECLinPS Circuit Performance at Non–Standard VIH Levels

AN1405

– ECL Clock Distribution Techniques

AN1406

– Designing with PECL (ECL at +5.0 V)

AN1503

– ECLinPS I/O SPICE Modeling Kit

AN1504

– Metastability and the ECLinPS Family

AN1560

– Low Voltage ECLinPS SPICE Modeling Kit

AN1568

– Interfacing Between LVDS and ECL

AN1596

– ECLinPS Lite Translator ELT Family SPICE I/O Model Kit

AN1650

– Using Wire–OR Ties in ECLinPS Designs

AN1672

– The ECL Translator Guide

AND8001 – Odd Number Counters Design

AND8002 – Marking and Date Codes

AND8020 – Termination of ECL Logic Devices

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