UPD72850A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72850A

IEEE1394 400Mbps PHY

NEC => Renesas Technology 

µPD72850A

CONTENTS

1. PIN FUNCTIONS ..................................................................................................................................... 7

1.1 Cable Interface Pins......................................................................................................................... 7

1.2 Link Interface Pins ........................................................................................................................... 8

1.3 Control Pins...................................................................................................................................... 8

1.4 IC........................................................................................................................................................ 9

1.5 Power Supply Pins........................................................................................................................... 9

1.6 Other Pins......................................................................................................................................... 9

2. PHY REGISTERS ................................................................................................................................... 10

2.1 Complete Structure for PHY Registers ........................................................................................ 10

2.2 Port Status Page (Page 000) ......................................................................................................... 13

2.3 Vendor ID Page (Page 001) ........................................................................................................... 14

3. INTERNAL FUNCTION .......................................................................................................................... 15

3.1 Link Interface.................................................................................................................................. 15

3.1.1 Connection Method............................................................................................................................... 15

3.1.2 LPS (Link Power Status)....................................................................................................................... 15

3.1.3 LREQ, CTL0,CTL1, and D0-D7 Pins .................................................................................................... 15

3.1.4 SCLK..................................................................................................................................................... 15

3.1.5 LKON .................................................................................................................................................... 16

3.1.6 Direct .................................................................................................................................................... 16

3.1.7 Isolation Barrier..................................................................................................................................... 16

3.2 Cable Interface ............................................................................................................................... 18

3.2.1 Connections.......................................................................................................................................... 18

3.2.2 Cable Interface Circuit .......................................................................................................................... 19

3.2.3 Unused Ports ........................................................................................................................................ 19

3.2.4 CPS....................................................................................................................................................... 19

3.3 Suspend/Resume........................................................................................................................... 19

3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 19

3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 19

3.4 PLL and Crystal Oscillation Circuit.............................................................................................. 20

3.4.1 Crystal Oscillation Circuit...................................................................................................................... 20

3.4.2 PLL ....................................................................................................................................................... 20

3.5 PC0-PC2, CMC................................................................................................................................ 20

3.6 RESETB........................................................................................................................................... 20

3.7 RI1, RI0 ............................................................................................................................................ 20

4. PHY/LINK INTERFACE.......................................................................................................................... 21

4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................. 21

4.2 Link-on Indication .......................................................................................................................... 22

4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ....................................................... 23

4.3.1 CTL0,CTL1 ........................................................................................................................................... 23

4.3.2 LREQ .................................................................................................................................................... 23

4.3.3 PHY/Link Interface Timing .................................................................................................................... 27

4.4 Acceleration Control...................................................................................................................... 28

4.5 Transmit Status.............................................................................................................................. 29

Data Sheet S14452EJ1V0DS00

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