UPD72850A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72850A

IEEE1394 400Mbps PHY

NEC => Renesas Technology 

BLOCK DIAGRAM

CMC

PC0

PC1

PC2

PORTDIS

PSEL

SUS/RES

LREQ

LPS

DIRECT

SCLK

LKON

CTL0

CTL1

D0

D1

D2

D3

D4

D5

D6

D7

Link

Interface

I/O

RESETB

CPS

Cable

Power

Status

µPD72850A

Arbitration

and Control

State Machine

Logic

Receive Data

Decoder and

Retimer

Transmit Data

Encoder

TpA0p

TpA0n

Cable

Port1

TpB0p

TpB0n

Cable

Port2

Cable

Port3

Voltage

and

Current

Generator

Crystal

Oscillator

PLL

System

and

Transmit

Clock

Generator

TpA1p

TpA1n

TpB1p

TpB1n

TpA2p

TpA2n

TpB2p

TpB2n

TpBias0

TpBias1

TpBias2

R0

R1

XI

XO

FIL0

FIL1

2

Data Sheet S14452EJ1V0DS00

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