K8P5616UZB データシートの表示（PDF） - Samsung
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K8P5616UZB Datasheet PDF : 60 Pages
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K8P5616UZB
Rev. 1.0
datasheet NOR FLASH MEMORY
8.0 PRODUCT INTRODUCTION
The K8P5616UZB is 256Mbit NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The
device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electri-
cally by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory archi-
tecture that divides its memory array into 256 blocks (64 Kw x 256). Programming is done in units of 16 bits (Word) or 8 bits (Byte). All bits of data in one
or multiple blocks can be erased simultaneously when the device executes the erase operation. The device offers page access time of 30ns with random
access time of 80ns supporting high speed microprocessors to operate without any wait states.
The command set of K8P5616UZB is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output enable (OE) and
write enable (WE). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are
sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which
controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations.
The K8P5616UZB is implemented with Internal Program/Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algo-
rithms are invoked by program/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified
addresses. The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation.
The K8P5616UZB has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY pin, Data poll-
ing of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode.
[Table 4] Operations Table
Operation
CE
OE
WE
WP/ACC
A0(A-1) ~
A23
DQ0 ~ DQ7
DQ8 ~ DQ15
BYTE = VIH
BYTE = VIL
RESET
Read
L
L
H
X
AIN
DOUT
DOUT
DQ8 ~ 14 = High-z
DQ15 = A-1
H
Stand-by
Vcc±0.3V
X
X
H
X
High-Z
High-Z
High-Z
Vcc±0.3V
Output Disable
L
H
H
X
X
High-Z
High-Z
High-Z
H
Reset
X
X
X
X
X
High-Z
High-Z
High-Z
L
Write
L
H
L
X1)
AIN
DIN
DIN
DQ8 ~ 14 = High-z
DQ15 = A-1
H
L = VIL (Low), H = VIH (High), AIN = Address in, DIN = Data in, DOUT = Data out, X = Don't care.
NOTE :
1) WP/ACC must be VIH when writing on the outermost block. (BA0 or BA255)
2) Address for word mode is AMax:0.
Address for byte mode is AMax:A-1.
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