EM78568 データシートの表示（PDF） - ELAN Microelectronics

部品番号

コンポーネント説明

一致するリスト

EM78568

8-BIT OTP MICRO-CONTROLLER

ELAN Microelectronics 

EM78P568

8-bit OTP Micro-controller

Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register

User can use IOC register to define input or output each bit.

PAGE1 (Data RAM data register)

7

6

5

4

3

2

1

0

RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0

R/W

R/W

R/W

R/W R/W

R/W

R/W

R/W

Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM’s data

The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit

0 ~ Bit 1 (RAM_B0 ~ RAM_B1).

RA (PLL, Main clock selection, Comparator flag, Watchdog timer, DAC input data buffer,

LCD option)

PAGE0 (PLL enable bit, Main clock selection bits, Comparator control bits, Watchdog timer enable bit)

7

6

5

4

3

2

1

0

IDLE PLLEN CLK2 CLK1 CLK0 CMPFLAG CMPREF WDTEN

R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

R

R/W-0 R/W-0

Bit 0(WDTEN) : Watch dog control bit

0/1 disable/enable

User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If

the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the

prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.

Bit 1(CMPREF) : Comparator’s reference voltage source selection bit

0 Comparator’s reference voltage is driven from internal bias resistor string. This reference voltage level

can be set by RD PAGE0 bit 0 ~ bit 5 (CMP_B0 ~ CMP_B5).

1 Comparator’s reference voltage is driven from external bias. This reference voltage input is CMP3/P65

pin. Also IOC6 PAGE1 bit 2(CMP63/P63) should be set to “1”.

Bit 2(CMPFLAG) : Output of the comparator

0 Input voltage < reference voltage

1 input voltage > reference voltage

Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits

User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.

PLLEN CLK2 CLK1 CLK0 Sub clock MAIN clock CPU clock

1

0

0

0

32.768kHz 447.829kHz 447.829kHz (Normal mode)

1

0

0

1

32.768kHz 895.658kHz 895.658kHz (Normal mode)

1

0

1

0

32.768kHz 1.791MHz 1.791MHz (Normal mode)

1

0

1

1

32.768kHz 3.582MHz 3.582MHz (Normal mode)

1

1

0

0

32.768kHz 7.165MHz 7.165MHz (Normal mode)

1

1

0

1

32.768kHz 10.747MHz 10.747MHz (Normal mode)

1

1

1

0

32.768kHz 14.331MHz 14.331MHz (Normal mode)

1

1

1

1

32.768kHz 17.913MHz 17.913MHz (Normal mode)

0 don’t care

don’t care 32.768kHz don’t care 32.768kHz (Green mode)

Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register

0/1 disable PLL/enable PLL

If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode

(low frequency, 32768 Hz).

__________________________________________________________________________________________________________________________________________________________________

* This specification are subject to be changed without notice.

14

01/31/2004 V4.7

Share Link: