UPD4990AC データシートの表示（PDF） - NEC => Renesas Technology

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UPD4990AC

SERIAL I/O CALENDAR & CLOCK CMOS LSI

NEC => Renesas Technology 

µPD4990A

° Test mode

In the test mode, data is output to the DATA OUT pin regardless of whether data has been input to OUT

ENBL.

There are two different test modes depending on the OUT ENBL data.

(1) Test mode 1 (OUT ENBL = 0)

8 192 Hz signals are set parallel in the counters for year, month, week, day, time, minute, and second.

There is no carry from these counters.

Year

counter

Month

counter

Week

counter

Day

counter

Time

counter

Minute

counter

Second

counter

8 192 Hz

(2) Test mode 2 (OUT ENBL = 1)

A 8 192 Hz signal is input to the second counter instead of the 1 Hz signal. There is carry from counters.

Year

counter

Month

counter

Week

counter

Day

counter

Time

counter

Minute

counter

Second

counter

8 192 Hz

Outputs from DATA OUT and TP OUT pins in different function modes are listed below.

MODE

REGISTER HOLD

REGISTER SHIFT

TIME SET

TIME READ

DATA OUT

1 Hz

LSB of shift register

LSB of shift register

1 Hz

TP

64 Hz

32 Hz

L Level

32 Hz

Others

By this command, TEST MODE is released.

8 192 Hz input to time counter

Test mode

8 192 Hz input to time counter

When the REGISTER HOLD command cancels the test mode, 64 Hz is output to the TP pin.

10

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