JANKCA1N5554US データシートの表示（PDF） - Unspecified

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JANKCA1N5554US

SEMICONDUCTOR DEVICE, DIODE,SILICON, POWER, RECTIFIER

Unspecified 

MIL-PRF-19500/420H

* TABLE II. Group E inspection (all quality levels) for qualification and requalification only - Continued.

Inspection

* Subgroup 8

Peak reverse power

Electrical measurement

Subgroup 9 1/

Resistance to glass

cracking

* Subgroup 10

Forward surge

Electrical measurement

Method

MIL-STD-750

Conditions

Sampling

plan

See 4.5.5 herein. Peak reverse power (PRM)= shall be

characterized by the supplier and this data shall be available

to the Government. Test shall be performed on each sublot.

During the PRM test, the voltage (VBR) shall be monitored to

verify it has not collapsed. Any collapse in VBR during or

after the PRM test or rise in leakage current (IR) after the test

that exceeds IR1 in table I shall be considered a failure to that

level of applied PRM. Progressively higher levels of PRM shall

be applied until failure occurs on all devices within the

chosen sample size to characterize each sublot.

1057 Step stress to destruction by increasing cycles or up to a

maximum of 25 cycles.

n = 45

4066

IFSM = 80 A(pk); 10 surges of 8.3 ms each at 1 minute

intervals, superimposed on IO = 2 A dc; VRWM = rated VRWM

(see col. 3 of 1.3). TA = +100°C.

See table I, subgroup 2 and table III herein.

22 devices

c=0

1/ The sample size for this step stress requirement shall be determined by the supplier. A statistically significant

sample size is required.

20

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