IS61C1024AL-12HI データシートの表示（PDF） - Integrated Silicon Solution

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IS61C1024AL-12HI

128K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C1024AL, IS64C1024AL

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)

Symbol

Parameter

-12 ns

-15 ns

Min. Max.

Min. Max.

Unit

tWC

Write Cycle Time

12 —

15 —

ns

tSCE1

CE1 to Write End

10 —

12 —

ns

tSCE2

CE2 to Write End

10 —

12 —

ns

tAW

Address Setup Time to Write End

10 —

12 —

ns

tHA

Address Hold from Write End

0—

0—

ns

tSA

Address Setup Time

0—

0—

ns

tPWE(3)

WE Pulse Width

10 —

12 —

ns

tSD

Data Setup to Write End

7—

10 —

ns

tHD

Data Hold from Write End

0—

0—

ns

tHZWE(4)

WE LOW to High-Z Output

—7

—7

ns

tLZWE(4)

WE HIGH to Low-Z Output

2—

2—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

3. Tested with OE HIGH.

4. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

7

Rev. B

01/24/05

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