DS28DS28E01-100 データシートの表示（PDF） - Maxim Integrated

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DS28DS28E01-100

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Maxim Integrated 

ABRIDGED DATA SHEET

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

Refer to the full data sheet.

Figure 6. Memory Protection Matrix

BIT # 7

6

5

4

3

2

1

0

TARGET ADDRESS (TA1) T7

T6

T5

T4

T3

T2

(0)

T1

(0)

T0

(0)

TARGET ADDRESS (TA2) T15

T14

T13

T12

T11

T10

T9

T8

ENDING ADDRESS WITH

DATA STATUS (E/S) AA

1

PF

1

(READ ONLY)

Figure 7. Address Registers

1

E2

E1

E0

(1)

(1)

(1)

Address Registers and Transfer Status

The DS28E01-100 employs three address registers:

TA1, TA2, and E/S (Figure 7). These registers are com-

mon to many other 1-Wire devices, but operate slightly

differently with the DS28E01-100. Registers TA1 and

TA2 must be loaded with the target address to which

the data is written or from which data is read. Register

E/S is a read-only transfer-status register used to verify

data integrity with write commands. Since the scratch-

pad of the DS28E01-100 is designed to accept data in

blocks of 8 bytes only, the lower 3 bits of TA1 are

forced to 0 and the lower 3 bits of the E/S register (end-

ing offset) always read 1. This indicates that all the data

in the scratchpad is used for a subsequent copying into

main memory or secret. Bit 5 of the E/S register, called

PF or partial byte flag, is a logic 1 if the number of data

bits sent by the master is not an integer multiple of

eight or if the data in the scratchpad is not valid due to

a loss of power. A valid write to the scratchpad clears

the PF bit. Bits 3, 4, and 6 have no function; they always

read 1. The partial flag supports the master checking

the data integrity after a write command. The highest

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