CS61884 データシートの表示（PDF） - Cirrus Logic

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CS61884

Octal T1/E1/J1 Line Interface Unit

Cirrus Logic 

CS61884

LIST OF FIGURES

Figure 1. CS61884 144-Pin Outs ....................................................................................................... 7

Figure 2. CS61884 160-Ball FBGA Pin Outs .................................................................................... 8

Figure 3. G.703 BITS Clock Mode in NRZ Mode .......................................................................... 23

Figure 4. G.703 BITS Clock Mode in RZ Mode ............................................................................. 23

Figure 5. G.703 BITS Clock Mode in Remote Loopback ............................................................... 23

Figure 6. Pulse Mask at T1/J1 Interface .......................................................................................... 24

Figure 7. Pulse Mask at E1 Interface .............................................................................................. 24

Figure 8. Analog Loopback Block Diagram .................................................................................... 30

Figure 9. Analog Loopback with TAOS Block Diagram ................................................................ 30

Figure 10. Digital Loopback Block Diagram .................................................................................. 31

Figure 11. Digital Loopback with TAOS ........................................................................................ 31

Figure 12. Remote Loopback Block Diagram ................................................................................. 31

Figure 13. Serial Read/Write Format (SPOL = 0) ........................................................................... 33

Figure 14. Arbitrary Waveform UI .................................................................................................. 43

Figure 15. Test Access Port Architecture ........................................................................................ 45

Figure 16. TAP Controller State Diagram ....................................................................................... 46

Figure 17. Internal RX/TX Impedance Matching ............................................................................ 51

Figure 18. Internal TX, External RX Impedance Matching ............................................................ 52

Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 ........................... 58

Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 ............................................ 58

Figure 21. Recovered Clock and Data Switching Characteristics ................................................... 60

Figure 22. Transmit Clock and Data Switching Characteristics ...................................................... 60

Figure 23. Signal Rise and Fall Characteristics ............................................................................... 60

Figure 24. Serial Port Read Timing Diagram .................................................................................. 61

Figure 25. Serial Port Write Timing Diagram ................................................................................. 61

Figure 26. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode ................... 63

Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode ........ 63

Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus .................. 64

Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus ................... 64

Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode ....... 66

Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode ........ 66

Figure 32. Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67

Figure 33. Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode . 67

Figure 34. JTAG Switching Characteristics .................................................................................... 68

DS485PP4

5

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