CS5460A-BS データシートの表示（PDF） - Cirrus Logic
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CS5460A-BS Datasheet PDF : 54 Pages
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CS5460A
ANALOG CHARACTERISTICS (Continued)
Parameter
Dynamic Characteristics
Phase Compensation Range (Voltage Channel, 60 Hz)
High Rate Filter Output Word Rate
(Both Channels)
Input Sample Rate
DCLK = MCLK/K
Full Scale DC Calibration Range
(Note 7)
Channel-to-Channel Time-Shift Error
(when PC[6:0] bits are set to “0000000”)
High Pass Filter Pole Frequency
-3 dB
Power Supplies
Power Supply Currents (Active State)
IA+
ID+ (VD+ = 5 V)
ID+ (VD+ = 3.3 V)
Power Consumption
(Note 8)
Active State (VD+ = 5 V)
Active State (VD+ = 3.3 V)
Stand-By State
Sleep State
Power Supply Rejection Ratio
for Current Channel
(Note 9)
(50, 60 Hz)
(Gain = 10)
(Gain = 50)
Power Supply Rejection Ratio
for Voltage Channel
(50, 60 Hz)
(Note 9)
PFMON Power-Fail Detect Threshold
(Note 10)
PFMON “Power-Restored” Detect Threshold (Note 11)
Symbol
OWR
FSCR
PSCA
PSCD
PSCD
PC
PSRR
PSRR
PSRR
PMLO
PMHI
Min
Typ
Max Unit
-2.4
-
+2.5
°
-
DCLK/1024
-
Sps
-
DCLK/8
-
Sps
25
-
100 %F.S.
1.0
µs
-
0.5
-
Hz
-
1.3
-
mA
-
2.9
-
mA
-
1.7
-
mA
-
21
25
mW
-
11.6
-
mW
-
6.75
-
mW
-
10
-
µW
56
-
75
-
-
dB
-
dB
48
-
-
dB
2.3
2.45
-
V
-
2.55
2.7
V
Notes: 7. The minimum FSCR is limited by the maximum allowed gain register value.
8. All outputs unloaded. All inputs CMOS level.
9. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sinewave
(frequency = 60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The “+” and “-” input
pins of both input channels are shorted to VA-. Then the CS5460A is commanded to ’continuous
computation cycles’ data acquisition mode, and digital output data is collected for the channel under
test. The zero-peak value of the digital sinusoidal output signal is determined, and this value is
converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the
channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as
Veq. PSRR is then (in dB):
PSRR
=
20
⋅
log
⎧
⎨
⎩
0----.-1----5---0----V--
Veq
⎫
⎬
⎭
10. When voltage level on PFMON is sagging, and LSD bit is 0, the voltage at which LSD bit is set to 1.
11. Assuming that the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), then if/when
the PFMON voltage starts to rise again, PMHI is the voltage level (on PFMON pin) at which the LSD bit
can be permanently reset back to 0 (without instantaneously changing back to 1). Attempts to reset the
LSD bit before this condition is true will not be successful. This condition indicates that power has been
restored. Typically, for a given sample, the PMHI voltage will be ~100 mV above the PMLO voltage.
6
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