CS5460A-BS データシートの表示（PDF） - Cirrus Logic
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CS5460A-BS Datasheet PDF : 54 Pages
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CS5460A
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(TA = -40 °C to +85 °C; VA+ = VD+ = +5 V ±10%; VREFIN = +2.5 V; VA- = AGND = 0 V; MCLK = 4.096 MHz,
K = 1; N = 4000 ==> OWR = 4000 Sps.)(See Notes 1, 2, 3, 4, and 5.)
Parameter
Accuracy (Both Channels)
Common Mode Rejection
Offset Drift (Without the High Pass Filter)
Analog Inputs (Current Channel)
Maximum Differential Input Voltage Range
{(VIIN+) - (VIIN-)}
Symbol
(DC, 50, 60 Hz) CMRR
(Gain = 10)
IIN
(Gain = 50)
Total Harmonic Distortion
Common Mode + Signal on IIN+ or IIN- (Gain = 10 or 50)
Crosstalk with Voltage Channel at Full Scale (50, 60 Hz)
Input Capacitance
(Gain = 10)
(Gain = 50)
Effective Input Impedance
(Note 6)
(Gain = 10)
(Gain = 50)
Noise (Referred to Input)
(Gain = 10)
(Gain = 50)
THDI
Cin
ZinI
ZinI
Accuracy (Current Channel)
Bipolar Offset Error
(Note 1)
Full-Scale Error
(Note 1)
Analog Inputs (Voltage Channel)
Maximum Differential Input Voltage Range {(VVIN+) - (VVIN-)}
Total Harmonic Distortion
Common Mode + Signal on VIN+ or VIN-
Crosstalk with Current Channel at Full Scale (50, 60 Hz)
Input Capacitance
Effective Input Impedance
(Note 6)
Noise (Referred to Input)
VOSI
FSEI
VIN
THDV
CinV
ZinV
Accuracy (Voltage Channel)
Bipolar Offset Error
Full-Scale Error
(Note 1) VOSV
(Note 1) FSEV
Min
80
-
-
-
80
-0.25
-
-
-
-
-
-
-
-
-
-
62
VA-
-
-
-
-
-
-
Typ
-
5
-
-
-
-
-
25
25
30
30
-
-
±0.001
±0.001
-
-
-
-
0.2
5
-
±0.01
±0.01
Max
-
-
500
100
-
VA+
-115
-
-
-
-
20
4
-
-
500
-
VA+
-70
-
-
250
-
-
Unit
dB
nV/°C
mVP-P
mVP-P
dB
V
dB
pF
pF
kΩ
kΩ
µVrms
µVrms
%F.S.
%F.S.
mVP-P
dB
V
dB
pF
MΩ
µVrms
%F.S.
%F.S.
Notes: 1. Bipolar Offset Errors and Full-Scale Gain Errors for the current and voltage channels refer to the respective Irms
Register and Vrms Register output, when the device is operating in ‘continuous computation cycles’ data acquisition
mode, after offset/gain system calibration sequences have been executed. These specs do not apply to the error
of the Instantaneous Current/Voltage Register output.
2. Specifications guaranteed by design, characterization, and/or test.
3. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted.
4. In requiring VA+ = VD+ =5 V ±10%, note that it is allowable for VA+, VD+ to differ by as much as ±200 mV, as long
as VA+ > VD+.
5. Note that “Sps” is an abbreviation for units of “samples per second”.
6. Effective Input Impedance (Zin) is determined by clock frequency (DCLK) and Input Capacitance (IC).
Zin = 1/(IC*DCLK/4). Note that DCLK = MCLK / K.
5
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